Presenting the future of VHDL design
Sigasi HDT is the compelling next-generation development environment for VHDL designers.
Sigasi HDT is an intelligent development environment (IDE). It differs from other development tools in that it contains an ultra-fast VHDL parser and compiler that runs transparently in the background. At any given moment as you make modifications, the tool fully understands the design in terms of VHDL concepts. This technology makes it possible to support a wide range of powerful features...
About this screenshot of Sigasi HDT
What can you see on the above screenshot?- Project Explorer View:
The Project Explorer gives a clear overview of your projects.
- Easy collaboration through Subversion integration.
- VHDL libraries are easy to use and clearly visualized.
- Transparent and automatic Makefile generation for ModelSim.
- VHDL Editor:
Sigasi HDT helps you read/review existing code and write reusable code, thanks to its fast internal background VHDL analyzer.
- Hover over any identifier to see its declaration.
- All occurrences of selected identifiers are automatically highlighted.
- Immediate feedback on syntax and semantic problems.
- Clear problem markers where the problems occur in the editor view.
- Quick Fixes for common VHDL problems (sensitivity list, unused signals, ...).
- Intelligent autocomplete.
- Outline View:
- Clear overview of your current VHDL file in VHDL terms.
- Add port or generic and all existing instantiations in your project are automatically updated.
- Synced with the editor view for easy navigation.
- Hierarchy View:
- Clear high level overview of your current design project.
- Design unit dependencies are automatically determined.
- Refactor the hierarchy of your design.
- Extra Views:
Extra views on your projects.
- Problems view: an aggregated view on all problems in your projects.
- Console view: output of external tools, such as ModelSim.
- Search view: VHDL-aware search results.
- History view: Subversion history of files.