Sigasi's Blog

Graphic Design is dead - long live Graphical Views


Historically, all electronics design was based on graphics. I remember hand-painting PCBs in High School and etching them in a FeCl3 solution. Lucky, I never had to draw individual transistors and masks sets in india ink. That time has long past as integrated circuits have become too complex to design one transistor at a time. Still, the concept that electronic circuits have to be visualized has somehow survived, long after the complexity of the largest ICs has surpassed what a single human brain can grasp.

Graphical design entry for VLSI design is dead.

Generating a Sigasi project from a Vivado project

I have blogged before on how to import Xilinx ISE projects in Sigasi before. In this blog post I show how you can import an existing Vivado project into Sigasi.

If you have a Vivado project which uses one or more IP cores, the project becomes complex quickly. Vivado generates different sources for Simulation and Synthesis. And although VHDL has elegant support for this –entities can have multiple architectures–, Vivado generates duplicate entities instead.

Be careful with VHDL operator precedence

I was recently writing some tests for our VHDL expression evaluator and was amazed by the the result of evaluting -16 ** 2.
I expected 256, but it wasn't.

Can you guess the output of running this process?

     process is
          report "-5 mod (-3) : " & integer'image(-5 mod (-3));
          report "(-5) mod (-3) : " & integer'image((-5) mod (-3));
          report "-(5 mod (-3)) : " & integer'image(-(5 mod (-3)));
          report "-16 ** 2 : " & integer'image(-16 ** 2);

Whitepaper: Standard Editor for Teams

This whitepaper explains why programmers tend to cling to the text editors they are used to using and are not always eager to move to a standardized product. Here we explain why a standardized text editor, one that is complete Integrated Development Environment (IDE), benefits the development organization.

Standardized Software

In the past, in Europe, each country’s railroads used a different width for their train tracks. When a train leaving, say, France, went into Spain, the train would have to stop and unload its cargo and load it onto a different train at the border.

Importing a Xilinx ISE project in Sigasi

Although project setup in Sigasi is in most cases straight forward, it remains a hurdle, certainly if you already have a 'project definition' in another tool. I have blogged about Scripting Sigasi project creation for importing custom project descriptions before. But now we extended the Python scripts to make even easier to import Xilinx ISE and Mentor Graphics HDL Designer projects. In this post I show how easy this has become.