Sigasi's Blog

This website hosts blogs on multiple topics that relate to the world, work and lives of Sigasi team members.

Sigasi HDT
All blog posts related to our product, Sigasi HDT: tips and tricks, howtos, feature discussions, ...
Jan on HDL design
Jan's blog about his personal views on HDL design. Relevant for the future, but aware of the past.
VHDL
Posts that will make you a better VHDL designer, regardless of the tools you use.
Developing for Eclipse
We develop on top of Eclipse, so we have some experience in this field. In this feed, we share some of this experience.

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VHDL word search puzzle

Posted Fri, 2010-04-23 12:58 by heeckhau

We shouldn't always be serious. With a good toolkit, VHDL can also be fun.
Although I'm afraid that Sigasi's recovering parser will not be able to recover from following fragment. So you will have to search manually, as in the good old days...

Can you find all words?
architecture, latch, code, register, component, reset, concurrency, sigasi, description, simulation, entity, end, statement, hardware, signal, synthesis, ieee, timing, inout, vhdl

Y C N E R R U C N O C A
T E S E R A W D R A H L
V S I G A S I G N A L A
H F R E G I S T E R C T
D E S C R I P T I O N C
L N I G N I M I T E O H
A R C H I T E C T U R E
E N D S Y N T H E S I S
T N E N O P M O C T N I
C O D E N T I T Y R O E
S I M U L A T I O N U E
G R S T A T E M E N T E

Did you find which word you can form out of the remaining 11 characters?

Why is GHDL (currently) not good enough?

Posted Mon, 2010-04-19 21:13 by pfaes

In my previous post I argued that the world would be a better place if we had a freely available VHDL parser and simulator. Today, I will explain why one particular open source compiler is honorable, but not sufficient.

If you have ever searched for a VHDL simulator, you will surely have found (and perhaps tried) GHDL. GHDL is an open source simulator for VHDL, implemented as a front-end for the popular GCC compiler. While it is the best open source alternative available at the moment, there are some problems with it.

GHDL supports only part of the VHDL language. While it behaves pretty decently for correct VHDL code, erroneous code may cause GHDL to crash without a sensible error message. This leaves the engineer in the cold, not knowing where he should start looking for the mistake he made. In order to improve GHDL to an industrial quality level, we need more developers working on it. Call it a developer community.
GHDL is written in ADA, a language that is hardly used, save by defense contractors. Having ADA as its project language, GHDL may have a hard time attracting code contributors. To its defense, ADA resembles VHDL. So it should be easy for VHDL designers to pick up ADA.

The activity level on the mailing list, the website and the Subversion repository is not exciting. GHDL is basically lead by a single developer, Tristan Gingold, with occasional help from others. I think Tristan has done a great job getting GHDL to where it is now, and I hear he is a very responsive project maintainer. However, it takes more than a project lead to build a community.

Considering its difficulties, I haven't given up on GHDL, but I would not bet my money on it either.

--
Philippe

Also read my next post.

Lacking an open source VHDL simulator

Posted Sun, 2010-04-11 20:25 by pfaes

The most important tasks of digital designers is to write VHDL (or Verilog) code and to verify it. The two tools you need for that are: an editor (or rather: an IDE) and a simulator. Editors are available for free and I've discussed IDE's elsewhere. What concerns me is that there are no high quality open source implementations of a VHDL simulator available.

Now, why is that a concern? I think there are two points to be made.

The first reason why we need an open reference implementation, is more important for me as an EDA tool vendor. We need an open VHDL parser and simulator, so that new players can innovate on VHDL technology. Today, any new company that wants to build a new VHDL tool, needs to write or buy their own parser. The price of a VHDL and Verilog parser from the leading provider is in the order of seven-digits. Not a problem for the top three EDA vendors or the two largest FPGA vendors, but the rest of us will think twice before spending that kind of money. Cheaper reusable parsers and open source parsers are just not good enough to build a commercial product. Universities using these parsers spend all their effort building a prototype that will yield interesting papers, but not a product they can spin off.

The second reason is that hardware designers should be able to choose a high quality low cost simulator. This will enable more people to work with VHDL and with FPGA's. I think the best way to deliver this is through an open source model. I think that other, more complex EDA tools, including synthesizers, require too much of an R&D effort to have them available in an open-source model, so let me focus on simulators. Perhaps we can get to synthesis tools in the next decade.

If there is to be more innovation in EDA, we need a freely available parser and simulator for VHDL, Verilog and SystemVerilog. Contrary to FSF dogma, GPL-style licenses will not provide enough freedom for EDA start up companies. These companies will want to sell their software under a proprietary license model. The least we need is LGPL, but BSD-style would be the best.

In my next post, I will talk about a popular, but not quite good enough VHDL simulator.

Let me know what you think in the comments, or on Twitter.

--
Philippe

Also read my next post.

How to sell EDA tools in Liechtenstein

Posted Thu, 2010-04-08 16:21 by pfaes

In the EDA sector, about 80% is turned over by the three market leaders, who have a tremendous world wide sales force. Does this market still allow new players to sell their products in different parts of the world? The only way to compete is not to compete: focus on the areas that large corporations are not good at.

Traditional sales

The traditional EDA direct selling process is very heavy weight. Many start-up companies with great products have a very hard time bringing the product to the market, boosting sales and bringing their company to profitability. The more their sales force grows, the more revenue is required to reach profitability.

Here are some of the problems with a traditional direct sales model.

  • The sales process may be long because it requires technology evaluations and prices negotiations.
  • Installing the software, even for an evaluation, is complex and time-consuming.
  • It may take a large effort to evaluate the a tool, and evaluation is only possible in a certain phase of the design process.

It is the best interest of large EDA vendors to focus on their bigger customers, which can produce more revenue for the same sales effort. This is a good example of Pareto principle of the Vital Few. In the past, when producing ASICs was reserved for a select elite of multinational corporations, this was surely the best strategy to take.
However, today we see an increasing number of small design teams, consisting of less than five engineers. The traditional heavy-weight direct selling method is inefficient to reach these Long Tail customers.

More Sales with Less Effort

In addition to direct sales in our local market of Belgium and the Netherlands, Sigasi focuses on web based sales and marketing. Web sales has important advantages compared to direct sales, but there are some strict boundary conditions.

Benefits

Web sales scale extremely well. In our early days, we sometimes wondered what would happen if our next press release would attract too many visitors to our website. If you sit down and do the math, you can easily see that there is no problem at all. Even if every VHDL designer in the world would visit our website in on week's time, a simple call to our web hosting company would give us enough compute power to serve them. Compare that to your sales team being flooded with phone calls. You would loose customers and it would takes weeks (or months) to hire and train new sales reps.

Another advantage is the low cost of sales. Our customers can choose to send us a purchase order, or just buy online using their credit card. Many corporate customers prefer the traditional sequence (price quote / purchase order / invoice / wire transfer). But especially smaller businesses and contractors prefer to pull out their credit card. The latter causes less paper work for everybody.

Conditions

Web sales only works under certain circumstances.

First you need good online marketing. We work with a mix of Google Adwords, SEO, blogging, white papers, twitter and press releases. If you haven't already, you should read Inbound Marketing.

Second, you need a price point that is acceptable for online sales, and thus for credit card transactions. Our price is set at 499€ for one person for one year, which can easily be paid using credit cards.

Third, it should be very easy to download, install and evaluate the software. Our customers sign up for a trial license on our website, and after a few minutes, they are up and running with the new tool. This is very different from some of the large EDA companies, where you request a trial license and nobody gets back to you. Installing is merely a matter of unzipping and we have a tutorial embedded in the tool to teach the basic principles.

Next, you have to be able to support the tool without leaving your desk. In this business you're lucky if your customer is in the same time zone. Without an army of Field Application Engineers (FAEs) in five continents, you need other means to provide high quality support. You need a product that produces just enough forensic data that customers can send back to you. You need to use all communication channels that help you in determining the problem: phone calls, Skype with screen sharing, twitter, emails of code snippets, sceenshots and screencasts, photographs of whiteboards. Anything works.

Lacking an army of sales people and FEAs is no excuse for not listening carefully to your customers. Rather, it is an opportunity to let the end users communicate directly with the decision makers and developers with your company. To us, it hardly matters if our customers are in the USA, Norway or in Liechtenstein.

Play on your own terms

Billion dollar companies are very good at many things. There is no use in trying to play along, let alone beat them at something they are good at. As an early-stage EDA company, we focus on our strengths and our flexibility. To us, web bases sales, which is not common in the world of EDA, is as important an innovation as our technology. While the big players focus only on very large customers, our strategy allows us to serve customers anywhere, and of any size.

Do More with Less

Harry "the ASIC guy" Gries (Xuropa) has asked us how Sigasi accomplishes "More with Less". This blog post explains how we generate sales without a large sales force. I share this information with the world, hoping that more people with good ideas start their own company and bring their technology to the market.
Please consider voting for this article on the Xuropa site.

How to run Xilinx ISim/Fuse from the command line on Linux

Posted Thu, 2010-04-08 09:19 by heeckhau

Xilinx no longer ships ModelSim with ISE but now ships its own HDL simulator that enables functional and timing simulations for VHDL, Verilog and mixed VHDL/Verilog designs: ISim.

I had some trouble setting up ISim from the command line on my Linux machine, so I documented how to use ISim here for future reference.

Install Xilinx ISE

First download and install the ISE software from the Xilinx Website. I installed Xilinx in /opt/Xilinx/11.1/.

Run Fuse to compile, elaborate and link your project

The command line tool that accompanies ISim is called Fuse. Fuse is the HDL compiler, elaborator and linker used by ISim. You can find this executable in your Xilinx installation folder in the binaries dir (/opt/Xilinx/11.1/ISE/bin/lin in my case).

This tool needs a few parameters:

  • A (.prj) project file with all source files (-prj)
  • Top level
  • Executable name (-o)
  • Optional parameters

The project file is a file (ending with .prj) with an entry for each file, plus its library.
For the Dirac OpenCores project that ships with Sigasi HDT, this is (Dirac.prj):

  1. vhdl work src/testbench/DECODERTESTBENCH.VHD
  2. vhdl work src/testbench/ArithmeticCoderTestbench.vhd
  3. vhdl work src/encoder/FOLLOW_COUNTER.vhd
  4. vhdl work src/encoder/OUTPUT_UNIT.vhd
  5. vhdl work src/encoder/ARITHMETICCODER.vhd
  6. vhdl work src/encoder/LIMIT_REGISTER.vhd
  7. vhdl work src/decoder/ARITHMETICDECODER.vhd
  8. vhdl work src/decoder/STORAGE_REGISTER.vhd
  9. vhdl work src/decoder/SYMBOL_DETECTOR.vhd
  10. vhdl work src/expgolomb/EXP_GOLOMB_DECODER.vhd
  11. vhdl work src/expgolomb/EXP_GOLOMB_COUNTER.vhd
  12. vhdl work src/common/FIFO.vhd
  13. vhdl work src/common/UPDATER.vhd
  14. vhdl work src/common/D_TYPE.vhd
  15. vhdl work src/common/COUNT_UNIT.vhd
  16. vhdl work src/common/STORE_BLOCK.vhd
  17. vhdl work src/common/INPUT_CONTROL.vhd
  18. vhdl work src/common/CONVERGENCE_CHECK.vhd
  19. vhdl work src/common/ARITHMETIC_UNIT.vhd
  20. vhdl work src/common/ENABLEABLE_D_TYPE.vhd
  21. vhdl work src/common/CONTEXT_MANAGER.vhd
  22. vhdl work src/common/Divider.vhd
  23. vhdl work src/common/HALVING_MANAGER.vhd

I choose Dirac as executable and the toplevel is DECODERTESTBENCH. I always add -intstyle ise -incremental as optional parameters. -intstyle ise makes sure Sigasi HDT can link error messages in the console view with the editor view. -incremental tells Fuse to only compile those files that have changed since the last compile; but I do not have the impression this really works.

My complete command is:

/opt/Xilinx/11.1/ISE/bin/lin/fuse -intstyle ise -incremental -o Dirac -prj Dirac.prj DECODERTESTBENCH

Run the simulation

Initially when I tried to run the generated executable (Dirac), I always got:

Segmentation fault

The solution was to set some environment variables:

export XILINX=/opt/Xilinx/11.1/ISE
export PLATFORM=lin
export PATH=$PATH:${XILINX}/bin/${PLATFORM}
export LD_LIBRARY_PATH=${XILINX}/lib/${PLATFORM}

Now you can run Dirac:

[heeckhau@elvis Dirac]$ ./Dirac
WARNING: A WEBPACK license was found.
WARNING: Please use Xilinx License Configuration Manager to check out a full ISim license.
WARNING: ISim will run in Lite mode. Please refer to the ISim documentation for more information on the differences between the Lite and the Full version.
This is a Lite version of ISim.
Time resolution is 1 ps
ISim> run 10 ns
Simulator is doing circuit initialization process.
at 0 ps, Instance /decodertestbench/UUT/INBUFFER/STORAGE/ : Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
at 0 ps, Instance /decodertestbench/UUT/INBUFFER/STORAGE/ : Warning: CONV_INTEGER: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, and it has been converted to 0.
at 0 ps, Instance /decodertestbench/UUT/PROBABILITY/ : Warning: CONV_INTEGER: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, and it has been converted to 0.
at 0 ps, Instance /decodertestbench/UUT/PROBABILITY/ : Warning: CONV_INTEGER: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, and it has been converted to 0.
Finished circuit initialization process.
at 5 ns(1), Instance /decodertestbench/UUT/PROBABILITY/ : Warning: CONV_INTEGER: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, and it has been converted to 0.

You can also start the gui from the command line:

./Dirac -gui

This works on our Centos machines, but not on my Fedora release 10 work station. I did not find out why yet, but it is probably due to Xilinx using an older version of GLIBC.

You can also start ISim with a tcl-script, such as:

./Dirac -tclbatch isim.cmd

where iscim.cmd is for example:
wave add DECODERTESTBENCH
run 10 ns

This should save you some time.

Coming soon

In the upcoming version of Sigasi HDT, we will generate all these scripts for you. That way you can focus on the design, and let the tools take care of the dirty work.

Some useful links

ISim Manual
In Depth tutorial
ISim FAQ

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