Sigasi's Blog

This website hosts blogs on multiple topics that relate to the world, work and lives of Sigasi team members.

Sigasi HDT
All blog posts related to our product, Sigasi HDT: tips and tricks, howtos, feature discussions, ...
Jan on HDL design
Jan's blog about his personal views on HDL design. Relevant for the future, but aware of the past.
VHDL
Posts that will make you a better VHDL designer, regardless of the tools you use.
Developing for Eclipse
We develop on top of Eclipse, so we have some experience in this field. In this feed, we share some of this experience.

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Vertical align

align.mov

Vertical alignment of VHDL code in Sigasi HDT.

The feature demonstrated in this video has been improved. See the new video for the current behavior of vertical align.








The biggest EDA innovations that did not happen

In my previous blog post, I concluded that RTL synthesis was the latest of the all-time most important EDA innovations. Although it is more than 20 years old, nothing with a similar impact has happened since.

It's not that there was a lack of candidates. In the early nineties, several ideas and technologies seemed to have great potential. Personally, I was eager to repeat my great experience with RTL synthesis. Moreover, my company was basically selling design methodology, so we had a vested interest to stay at the forefront of innovation. Consequently, we were continuously watching out for the next big thing. But it didn't come. So here is my personal anti-list: the biggest EDA innovations that did not happen.

First on my list is Asynchronous Design Synthesis. Asynchronous design refers to design techniques without a global clock. It promises advantages with regard to performance, power consumption and design security, but it is inherently more complicated than synchronous design.

Then comes Formal Verification. Formal verification refers to the use of mathematical proof to verify the correctness of a design. When it works, it is superior to simulation, because it provides a 100% guarantee.

Last but not least we have Behavioral Synthesis. This is a technique whereby one starts from an algorithmic description, and where a synthesis tool allocates hardware resources and assigns operations to clock cycles.

Let me be clear about my position. I certainly don't want to suggest that there hasn't been any progress in the listed domains. Quite the contrary. There are now EDA tools that support a systematic methodology for asynchronous design. Formal verification tools are being employed successfully for certain well-defined tasks in the design flow. And behavioral synthesis is moving into the spotlight with the new wave of C-based high level synthesis tools.

What I am saying is that these tools have not fundamentally changed the way in which the majority of design engineers work. The mainstream paradigm for digital circuitry and EDA is still synchronous design. To verify the functionality of complex designs, we are still using good old simulation, not formal verification. And behavioral synthesis hasn't replaced RTL synthesis as the principal synthesis technique in mainstream design flows.

In summary, none of these tools has revolutionized the industry in the way RTL synthesis did.

How to automatically run the ModelSim Makefile in Sigasi HDT?

Sigasi HDT automatically and transparently analyzes your VHDL code in the background while you are designing. Sigasi's objective is to do this as fast as possible to give you real-time feedback. Of course you also still have to simulate your code with a VHDL simulator such as ModelSim. Since a few months, Sigasi HDT can automatically create and update a Makefile to compile your project with ModelSim. And through the use of a builder it is also possible to automatically run this Makefile when you make changes to your design. In this blog post I will explain how.

First verify that vcom and vlib are on your path or add it (export PATH=/opt/altera9.0/modelsim_ase/bin/:$PATH on my machine).

Next make sure that Sigasi HDT creates the Makefile:
Click Window > Preferences > VHDL > Makefiles, enable Mentor Modelsim (vsim) and confirm with OK

The Makefile is generated when you perform a full (re)build of your project. Click Project > Rebuild project to force this build. The Makefile.vsim should appear in the Project Explorer now.

Next you have to add a builder to your project that will automatically execute the Makefile.

Right-click your project (the dlx-project in this example) and select Properties > Builders.

Click New...

Select Program as Configuration Type

Next, configure the builder:

  • Give your builder a name: e.g. ModelSim.
  • Enter "/usr/bin/make" as the location of the program to run.
  • Click Select Workspace to set the Working Directory and select the root of your project (${workspace_loc:/dlx} for my project)
  • Next enter as arguments: --makefile=Makefile.vsim all

With the default settings the ModelSim Makefile will only be run during a manual build or after a "Clean". To make sure Sigas HDT runs make every time you save a changed file, click the build options tab and enable the During auto builds checkbox.

When you close the builder configuration dialog windows, make will automatically be run, and Modelsim's messages will appear in the console view.

Note that warnings and errors in the console are clickable. If you click a message, the corresponding location will automatically be opened in the Editor view.

Hendrik

P.S.: You can add as many extra builders as you want this way. E.g. for extra linting, code generators,...

How to implement "highlight matching brackets" for your custom editor in Eclipse

For our VHDL editor view I wanted to implement highlight matching bracket like it exists in JDT. I had to dig a lot longer in the JDT code than anticipated to find out how JDT implements this functionality. As so often is the case in Eclipse development, in the end this turned out to be really easy. It was again a matter of finding with few lines to add...

The key is to override the configureSourceViewerDecorationSupport method from AbstractDecoratedTextEditor in your editor class and call the setMatchingCharacterPainterPreferenceKeys method. Note that the method name contains character and not bracket, which explains why I had to look so hard to find it.

public final static String EDITOR_MATCHING_BRACKETS = "matchingBrackets";
public final static String EDITOR_MATCHING_BRACKETS_COLOR= "matchingBracketsColor";
 
@Override
protected void configureSourceViewerDecorationSupport (SourceViewerDecorationSupport support) {
	super.configureSourceViewerDecorationSupport(support);		
 
	char[] matchChars = {'(', ')', '[', ']'}; //which brackets to match		
	ICharacterPairMatcher matcher = new DefaultCharacterPairMatcher(matchChars ,
			IDocumentExtension3.DEFAULT_PARTITIONING);
	support.setCharacterPairMatcher(matcher);
	support.setMatchingCharacterPainterPreferenceKeys(EDITOR_MATCHING_BRACKETS,EDITOR_MATCHING_BRACKETS_COLOR);
 
	//Enable bracket highlighting in the preference store
	IPreferenceStore store = getPreferenceStore();
	store.setDefault(EDITOR_MATCHING_BRACKETS, true);
	store.setDefault(EDITOR_MATCHING_BRACKETS_COLOR, "128,128,128");
}

Bracket highlighting is configured by two preference keys in a key store: one for enablement and one for the color of the box around the matched bracket. In the above code fragment I forced matching bracket highlighting with store.setDefault(EDITOR_MATCHING_BRACKETS, true); in neutral gray (store.setDefault(EDITOR_MATCHING_BRACKETS_COLOR, "128,128,128");).

I hope this can save you some time,
Hendrik.

Next Belgian Eclipse User Group Meeting (Tuesday February 23)

The program for the next Belgian Eclipse User Group is ready.

We present Yuri Kok and Wim Jongman, who will introduce us to Eclipse 4.
We are also eagerly looking forward to the presentations of our fellow community members.

Attendance is free, but registration is required and the number of participants is limited.

See you on Tuesday February 23th, 18h00 at PeopleWare in Lier.

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