Sigasi's Blog

This website hosts blogs on multiple topics that relate to the world, work and lives of Sigasi team members.

Sigasi HDT
All blog posts related to our product, Sigasi HDT: tips and tricks, howtos, feature discussions, ...
Jan on HDL design
Jan's blog about his personal views on HDL design. Relevant for the future, but aware of the past.
VHDL
Posts that will make you a better VHDL designer, regardless of the tools you use.
Developing for Eclipse
We develop on top of Eclipse, so we have some experience in this field. In this feed, we share some of this experience.

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Academic frustration

In my previous blog post, I told you that back in 1990 I got pretty excited about my first experiments with Synopsys Design Compiler.

To understand my excitement better, let me explain where I was coming from. After I graduated in 1985, I had worked for 2.5 years at the brand new IMEC institute in Leuven, Belgium. I was part of a team that did research on behavioral synthesis, in a project called the Cathedral silicon compiler. I remember well how we thought about the state of the field. Logic synthesis was considered a solved problem. The next big thing was "obviously" going to be behavioral synthesis. However, this is a very complex problem. Therefore (so the argument went) you have to choose a particular application domain to make it tractable. In our case, the application domain was DSP.

There were several clever people in the team doing clever things. But I remember that I often got a feeling of dissatisfaction. The choice of an application domain seemed artificial and arbitrary. Moreover, our behavioral synthesis tool needed a lot of manual steering through so-called "pragma's". As a result, it often seemed that the tool was not just restricted to an application domain, but to a single example.

Synopsys Design Compiler was a totally different kind of tool. It didn't need to know about the application domain: you could use it for just about any kind of digital design. Moreover, it came up with a good solution by default: pragma's and settings were only required to further optimize an already good solution. I felt relieved: this was silicon compilation according to my taste!

I can hear the critique already. What's the point in comparing a research project on behavioral synthesis to a commercial tool that surely works at a much lower level? Isn't this comparing apples to oranges? Well, I have a lot more to say about that, but I'll leave it for future posts. But in some sense the critique is definitely valid. As a result, my main conclusion out of this experience was that I'm probably not suited for an academic career. I didn't realize it at the time, but what I missed was a direct link to industry and customers.

I guess I always felt more at ease in the bazaar than in the cathedral.

Free tutorial webinar on December 15th

You have downloaded and tried Sigasi HDT? You have discovered some of its nice features, but you have the feeling there is a lot more to explore? This free webinar shows you the most important productivity features, so you can make the most out of using the VHDL tool of the future: Sigasi HDT.

Synthesis was my first love

In my previous blog post I mentioned that when I first met VHDL, it wasn't love at first sight. However, I did experience love at first sight with another hardware design technology: synthesis.

It was early 1990, and I had just started as a hardware designer at Alcatel. My very first assignment was an evaluation of a new tool called Synopsys Design Compiler. Within a few days after I got my hands on it, I was hooked. This was a tool that could convert a non-trivial hardware description "program" into an efficient implementation. I felt that I had discovered the missing link in the vision that hardware design is a kind of software development.

I remember that I tried out one Verilog example after another on the tool. Each time I thought: "it won't be able to handle this one". Yet each time the tool surprized me as it came back with a correct, efficient implementation. And on every occasion, my conviction grew that this was "it". I just "knew" that this tool was going to revolutionize the industry. I have been wrong with many predictions, but with this one I have been absolutely right.

Experimenting with Synopsys Design Compiler was a great experience, a time full of excitement and new insights. Only a few other technologies have made a similar first expression on me. Among them are the Netscape browser and the Python programming language, but Synopsys DC is still my number one. Such an experience does not happen every day, but it may have profound implications. It may change your life.

Synopsys Design Compiler did change my life. Without it, I wouldn't have bothered learning Verilog or VHDL, and I probably would have left the hardware design field a long time ago. Most importantly, I might never have started a company.

Free Webinar: A walk through Sigasi HDT

You have downloaded and tried Sigasi HDT? You have discovered some of its nice features, but you have the feeling there is a lot more to explore?

This free webinar shows you the most important productivity features, so you can make the most out of using the VHDL tool of the future: Sigasi HDT.

Sign up now, and join us on Wednesday, 2009-12-09 at 19:00 UTC.

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