News

  • Webinar: Boost VHDL development time with background design rule checking

    Online Webinar Thursday, November 30, 2017 3:00 PM – 4:00 PM (CET) Design rule checking (DRC) is a battle-proven method…

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  • The recording of the Sigasi Studio 3.6 Demo

    Sigasi Studio 3.6 Demo In case you have missed the Webinar, you can now watch the recording of the Sigasi…

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  • Register for the Sigasi Studio 3.6 demo

    Learn about the new features of Sigasi Studio 3.6 in our Webinars   We are organising a webinar to demonstrate the…

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  • The pictures @ Demo Night #FPL2017

    FPL came to Ghent this year, our hometown. We took some pictures on Demo Night, the pizzas were sponsored by…

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  • Sigasi supports #FPL2017

    September 4 – 8, Ghent   From September 4 until September 8, the 27th International Conference on Field Programmable Logic and Applications (FPL) takes…

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  • Enlist your team for the Electroniad Quiz

    Sigasi is proud to be the Silicon Sponsor at the 2nd Electroniad Quiz that takes place on September 14. Enlist…

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  • Visit us at the FPGA-Kongress in Munich

    Sigasi is going to the FPGA – Congress 2017 in Munich from Tuesday 11th until Thursday 13th of July.

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  • The recording of the Sigasi Studio 3.5 demo

    In case you have missed the Webinar, you can now watch the recording of the Sigasi Studio 3.5 Demo.  

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  • Full System Verilog Support: Sigasi in the news

    We have grouped all the links to articles and interviews that were published after Sigasi Studio 3.5 was released with…

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  • Sigasi makes the GarySmithEDA shortlist of “What to See at DAC 2017”

    This year we’ve made it to the 22nd shortlist of GarySmithEDA “What to see @ DAC”. Out of 148 exhibiting companies,…

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