Custom VHDL code formating
A few people asked me recently if the VHDL code formater in Sigasi can be customized to their code style. So I decided to write a blog post about so it can easily be Googled.
Can the formatter of Sigasi be customized? (The short answer is No. The long answer is Yes.)
Technically speaking we (the Sigasi developers) can easily modify code formatting. But we did not create a user interface to do this. The reason is that there are so many rules (and corner cases). So creating a UI to customize formatting would be a too much work for the added value it brings. So at this time, you can not customize Sigasi's formatting rules (except for the use of spaces vs. tabs).
However if you want a custom style (that differs from the Sigasi default), we can implement this custom style for you. We can even implement type-time linting checks that verify that all coding guidelines are respected. Contact us for more information.