Why is GHDL (currently) not good enough?
In my previous post I argued that the world would be a better place if we had a freely available VHDL parser and simulator. Today, I will explain why one particular open source compiler is honorable, but not sufficient.
If you have ever searched for a VHDL simulator, you will surely have found (and perhaps tried) GHDL. GHDL is an open source simulator for VHDL, implemented as a front-end for the popular GCC compiler. While it is the best open source alternative available at the moment, there are some problems with it.
GHDL supports only part of the VHDL language. While it behaves pretty decently for correct VHDL code, erroneous code may cause GHDL to crash without a sensible error message. This leaves the engineer in the cold, not knowing where he should start looking for the mistake he made. In order to improve GHDL to an industrial quality level, we need more developers working on it. Call it a developer community.
GHDL is written in ADA, a language that is hardly used, save by defense contractors. Having ADA as its project language, GHDL may have a hard time attracting code contributors. To its defense, ADA resembles VHDL. So it should be easy for VHDL designers to pick up ADA.
The activity level on the mailing list, the website and the Subversion repository is not exciting. GHDL is basically lead by a single developer, Tristan Gingold, with occasional help from others. I think Tristan has done a great job getting GHDL to where it is now, and I hear he is a very responsive project maintainer. However, it takes more than a project lead to build a community.
Considering its difficulties, I haven't given up on GHDL, but I would not bet my money on it either.
--
Philippe
Also read my next post.
Comments
I think the best direction
I think the best direction for an open-source simulator would be to abandon ADA. I don't see any reason we can't write a VHDL compiler in C. I think we just need a community with the will to do it.
What about a higher level language like Python? It would be the ultimate if MyHDL could be given a nicer path to simulation (beyond GtkWave). Why not build a Python based GTK application that hooks into simulations of MyHDL?
I took an advanced synthesis and place&route algorithms class in college. I don't really see any barrier to building a tool that can synthesize directly from MyHDL to an EDIF netlist. Has any work been done on this? To my knowlege not other than first converting to VHDL or Verilog.
Why not build a Python based GTK application that hooks into simulations of MyHDL?
Obviously this is a digression from the original focus, but why not just leapfrog VHDL and Verilog?
An additional problem with
An additional problem with GHDL is that it relies heavily on GCC's technology to produce executables. IMO, this makes GHDL hard to maintain and even compile.
A major drawback of GHDL is it's (lack) of speed. Commercial simulators are much faster. For small projects GHDL is fine, but for embedded systems containing one or more processors, it is simply too slow.
I often use GHDL because there is no other free simulator; Tristan has done a great job almost by himself and he is indeed a responsive project maintainer. But I would like a simulator coded in C or C++ so that I can contribute.
While ADA is not a hard language to learn, the compilers are often broken and support to fix things is lacking.
If someone, experienced in the art of VHDL simulation, were to start writing a simulator, I would be willing to contribute.
Hi Niels, You've raised two
Hi Niels,
You've raised two valid points about GHDL: maintainability (not easy to compile) and speed. Different groups of people will have trouble with different issues.
The electrical engineer who designs digital circuits will have no interest in how to compile GHDL. He only wants a tool that works fast enough. On the other hand, people that design small circuits, targeted at FPGAs, may be quite satisfied with GHDL's simulation speed. People designing large SoCs or ASICs are more likely to have a budget for simulators and synthesis tools.
I think the more important issue is maintainability. I would like to see an open-source community working on this simulator. I would like EDA start-ups to build on this technology, so that they can challenge the large EDA corporations. In order for this to work, the project should be very easy to recompile and to maintain.
As for the choice of application language: my heart lies with Java. Java will score better on the maintainability criterion, but C may result in a faster simulation. Anyway, (before we get into a religious war on application languages) the most important assets will probably not be the application itself, but the grammar, the test suite and the algorithms behind the application. Once we have that, it will be possible for anybody to re-implement in their language of choice.
My final year project is to
My final year project is to develop the VHDL simulator base on C,
After reading this post and the comments,
I am thinking to start the project with the VHDL compiler.
Are there any existing community or project that could help shed me some light?
You should have a look at
You should have a look at following projects:
The Hamburg VHDL archive also has some good pointers on VHDL parsers/compilers.
Good luck with your project,
Hendrik.
As for maintainability, look
As for maintainability, look at GCC frontend for LLVM: http://llvm.org/docs/GCCFEBuildInstrs.html
It can compile Ada to LLVM. Probably it is not a huge task to make GHDL work for LLVM too. LLVM has its own type system and byte code, making it easier to interoperate with other languages. Finally I understand what all the fuss about System Verilog is about. It's used for verification. Something Java, Objective C, C++, Python or any other language could be used for. LLVM could be used to facilitate such interconnects between VHDL (via GHDL) and any other language LLVM runtime has support for.