Note
An interactive version of this tutorial can be accessed inside Sigasi HDT by selecting Help ‣ Cheat Sheets ‣ Sigasi HDT -> The Sigasi HDT Tutorial
Sigasi HDT is the compelling next-generation development environment for VHDL designers.
Sigasi HDT is an intelligent development environment (IDE). It differs from other development tools in that it contains an ultra-fast VHDL parser and compiler that runs transparently in the background. At any given moment as you make modifications, the tool fully understands the design in terms of VHDL concepts. This technology makes it possible to support a wide range of powerful features:
All these features create a novel user experience that greatly improves productivity.
The last feature that was mentioned, refactoring, is Sigasi HDT’s most innovative and powerful functionality. Refactoring is a modern software development technique. Sigasi HDT implements it for digital hardware design.
Refactoring makes a new level of automation available to the designer. You can use it to make code clearer and more reusable, to find bugs, and to prepare code for adding new functionality. Examples of refactorings are:
Refactoring is a large topic on itself. For that reason, we have written a dedicated book about it: The VHDL Refactoring Book.
This tutorial will introduce you to the basic concepts of Sigasi HDT.
You will learn how to:
The tutorial is conceived to demonstrate all features, while being as lightweight and simple as possible. We will work on an incomplete design, which conveys the idea of a “design in progress”, with just 3 files:
Structure of the tutorial design. In this tutorial we make the clock_generator generate a second clock and connect this clock signal to the dut.
In this tutorial we will first demonstrate how to easily navigate through this design and show how to fix common problems. Next we will add functionality. We will reuse the clock driving process, so that the clock_generator will drive two clock signals with different frequencies. Then we will connect this second clock to the dut.
Before taking the tutorial, Sigasi HDT should be installed and properly configured. If this is not yet done you can find the instructions in Setting up Sigasi HDT.
To take the tutorial, the tool should be up and running. Start the hdt application using the appropriate method for your platform.
Now, we will import a project for the tutorial. Select File ‣ Import ‣ General ‣ Existing projects into Workspace and click Next. In the Import Projects window, choose Select archive file. and click Browse.... Using the file browser, go to folder exampleProjects on your disk or CD-ROM and select the tutorial.zip file. Afterwards, click Finish. Sigasi HDT now unzips the tutorial project in your workspace and opens it as new project.
In the leftmost window, check that the tutorial project folder is now listed. If you expand the project folder and the src folder within it, you will see a number of VHDL files.
After you open a design, you should see five views in Sigasi HDT:
Sigasi HDT when the tutorial project is opened. By default, HDT displays five different views.
The leftmost view in the user interface is the Project Explorer view. It shows a hierarchical representation of all project folders in the workspace. Expand the tutorial project and the src folder within it. Select the testbench.vhd file by double-clicking. Note that the contents of some other views changes. Their function is explained next.
The main view in the center is the Editor view. In this view, you can review and edit the text contents of the currently selected file.
In the Editor view, type some characters. Then, undo your typing automatically by selecting Edit‣Undo Typing. Note that Sigasi HDT suggests to use Ctrl-Z as a shortcut for this operation. Try the shortcut by typing some characters followed by Ctrl-Z.
In future tasks in this tutorial, Sigasi HDT may sometimes suggest shortcut keystrokes that you can use as an alternative to menu-based operations. Shortcuts can enhance productivity.
The top right view is the Outline view. It displays the contents of the currently selected file in terms of VHDL objects, grouped into Declarations and Statements. If you select a VHDL object in this view, the focus in the Editor view changes accordingly. Try that for a few objects.
Right below the Outline view is the Hierarchy view. It displays the VHDL design hierarchy below the top level object in the currently selected file. If you double-click an object in the hierarchy, the Editor view is updated accordingly, possibly by displaying the contents of a different file. You can go ahead an try it out.
The view in the bottom is Problems view. It displays the problems found in the design, such as warnings and errors. Note that there are a few warnings in the design. We will come back to those later.
Sigasi HDT makes it trivial to review the declaration of a given identifier.
Select the dut.vhd file using the Project Explorer view. In the Editor view, scroll down to a VHDL process. Look for the identifier clock and hold your mouse pointer over it. After a moment, a popup shows you the name and datatype of the object. This technique is called hovering. Try hovering your mouse over other identifiers and see which information is displayed.
We will now demonstrate how easy it is to navigate through your VHDL code.
Select the file testbench.vhd and look for the clock generator instantiation. Left-click to select the identifier clock_generator. Then, right-click and select Open Declaration. Note how the editor immediately switches to the file with the clock generator entity. To go back to the original file, press Navigate ‣ Back or Alt-Left.
Opening a declaration
Of course, navigation to a declaration works within a file also. Try it on a few identifiers.
With Sigasi HDT, it is easy to find references to a VHDL object in different files.
Select the file clock_generator.vhd. In the entity declaration, left-click to select the identifier clock_generator. Then, right-click and select Search References. A search window appears, displaying all references to the clock_generator, including those in other files. This makes it easy to see where a given VHDL object is used. You can browse through the references by using the arrow buttons on top of the search view. You can also navigate to each occurrence by double clicking the corresponding entry in the search view. Note that all references are highlighted.
Sigasi HDT can help you to improve code, through its automated refactorings. In this section, we will learn about the Rename refactoring.
Select the testbench.vhd file. Note in the instantiation statements that all actual signal names are identical to the formal port names. In particular, data_in and data_out are good names for ports of the dut entity, but not necessarily for the signals that connect to them. To convey their purpose it would be better to rename them to data_raw and data_stable.
Before continuing, think for a moment how you would do the renames with your current development tool.
In the dut instantiation, click on the actual signal data_in. Right-click and select Rename. In the pop-up window, fill in the new name data_raw. Select Preview to review the proposed changes. Click Ok to apply them.
As you can see, the tool renames the actual signal in the instantiation and in the signal declaration. However, the formal port is not modified, even though it had the same name originally. Like all functions in Sigasi HDT, Rename is intelligent: it knows which objects are involved from the design context.
Practice your skills by renaming the data_out signal to data_stable in the same way as in the previous section.
Rename is an example of a “refactoring”. Refactorings are techniques that improve the code structure without modifying its behavior. Sigasi HDT makes a wide range of automatic refactorings available.
Sigasi HDT can help you to detect problems. In addition, some problems can be resolved automatically using a so-called quickfix.
Select the dut.vhd file. In the Editor view, you see three warning
marker icons 
(on line numbers 19, 23 and 34) in the left
margin. Hover over each of the markers and figure out why the tool
complains about these lines of code. One marker indicates an unused
signal. The other two markers indicate incorrect sensitivity lists.
Each of the markers in this file has a light bulb in its icon. This
light bulb indicates that the tool can suggest an automatic solution
for the problem.
Put your cursor on the first warning marker, about the unused signal. Click on it. In a pop-up window, the tool proposes to solve the problem by the Remove declaration quickfix. Double-click on it to execute it, and note how the declaration disappears.
Put your cursor on the next warning marker and click on it. The tool proposes the quickfix Correct sensitivity list. Double click on it and see how the missing signal is added to the sensitivity list.
There is now one warning marker left. As an exercise, review the problem and solve it using the proposed quickfix.
Select the testbench.vhd file. Note the warning marker on line 25. The tool complains about a missing signal declaration for data_in. Use the quickfix to add it. Note that the correct datatype and width are inferred automatically.
Now we will demonstrate how you can use Sigasi HDT to extend a design.
What we want to do next is implement a new feature. Our design goal is to introduce a second clock, driven by the clock generator and going to the design-under-test. We will do this by a sequence of small modifications. Several of them are automatic refactorings.
Navigate to the clock generator. In the outline view, right click the clock generator entity and select Add port.
Adding a port
In the pop-up window, fill in the port name clock2 and a datatype std_logic for the new port. Use Preview to confirm that a new port will be added to the clock generator. Note also that the port map in the testbench is updated to include the new port. Since this is an out port, the updated portmap leaves the new port open. Press OK.
Now that we have created a second port for the clock generator, we want to drive that port. Instead of copy-pasting the existing clock driver process, we will encapsulate it so that it becomes a reusable component.
In the outline or hierarchy view, right click the clock driver process and select Encapsulate in new entity. Fill in the name clock_driver for the new entity and BEH for its architecture. Use Preview to check that this refactoring involves modifications to multiple files.
Preview for encapsulate refactoring.
A new file clock_driver.vhd is created with the process we wanted to encapsulate. Note that the tool infers the datatype and direction the port clock, and turns the constant PERIOD into a generic. Also, the original process in the clock generator is replaced by an instantiation of the newly created clock driver. Press OK.
You can also encapsulate multiple processes and instantiations in a new entity. To do this, just select multiple processes or instantiations in the hierarchy view before starting the refactoring.
The clock driver is now a reusable component, which we will instantiate a second time. Navigate to the clock generator and place your cursor on a new line below the first instantiation of the clock driver. Start entering a new instantiation by typing clock_driver_inst2: entity. At this point, press Ctrl-Space to request code completion. A list of all available entities pops up. Select the clock_driver entity and press Enter.
Press Ctrl-Space to activate the intelligent autocomplete.
The fields that you have to fill in are indicated and you can cycle through them using kbd:Tab. Fill in PERIOD2 and clock2 for the actual parameters. Press Enter.
Use Tab to cycle through the fields and Enter when done.
When you save the file after completing the instantiation, a red error marker will appear next to the generic map. Hover your mouse over the error marker to see the error message: Declaration of PERIOD2 could not be found.
We have to add a declaration similar to the following at the beginning of the architecture:
constant PERIOD2: time := 10 ns;
Again, code completion can help. Start by typing a few characters of constant and press Ctrl-Space. Select Declare a constant. Again, use Tab to cycle through the fields and complete them and press Enter when done.
After adding port clock2 and constant PERIOD2 to the clock generator, it would be more consistent to rename port clock to clock1 and constant PERIOD to PERIOD1. We can do these renames using the Rename refactoring that we learned earlier. Place your cursor on the identifier to rename and right click. Select Rename and type in the new name.
Rename refactoring
Recall that Rename is a refactoring that works on VHDL objects in the design instead of identifiers in a file. For example, note that the formal generic PERIOD is not renamed. On the other hand, port clock is also renamed in the test bench. Renaming is error prone with traditional editors, but with Sigasi HDT you shouldn’t hesitate to use the Rename refactoring to make code clearer.
To complete our design goal, we can connect the new clock output port from the clock generator to the dut instance. Conceptually, this is an elaborate operation with a number of steps:
Sigasi HDT can perform all these operation in one go. Navigate to the testbench, and right-click the DUT instance in the outline view or in the hierarchy view. Select Connect instance to.... In the list of available signals and ports, select port clock2 from the clock generator. All the steps described above are performed by the refactoring.
You have acquired some basic skills in using Sigasi HDT, and you are ready to practice your new skills on your own projects. Your next step is to learn how to create new projects in Sigasi HDT. This is explained in Setting up a project in the Sigasi HDT User Manual.
From now on, the Sigasi HDT User Manual is your first stop to learn more about Sigasi HDT. This manual is integrated in the tool itself. Just click Help ‣ Help Contents and double-click Sigasi HDT to navigate to the online user manual.