Sigasi HDT does not attempt to check full correctness of your VHDL code. We just run a set of syntax checks and general "sanity checks". This way, 90% of the common errors are caught before you even start your simulator.

As you design, you put your code through a funnel: first sigasi finds the first 90% of errors in your code, without ever running a simulation. Next you compile with the simulator and you find another bunch of problems. In each successive step of your design flow, you find harder to track errors in your design. Sigasi just helps you get a big number of issues out of the way early on, so that you can concentrate on finding the hard problems down the road.
Funnel of where to catch errors