In VHDL, certain identifiers (names) can be used more than once in the same scope. This is true for procedure names, function names and enumeration literals. These identifiers are overloadables.

Today, we do not have complete support for overloadables. Overloadables cannot be renamed, and the search function and open declaration may not work if there are indeed multiple candidates with the same name.

We will support type analysis and overloadables in a future version, but for now, this is still work in progress.