LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
--synthesis translate_off
Library XilinxCoreLib;
--synthesis translate_on
ENTITY ram_samples_255x16 IS
	port (
	clka: in std_logic;
	ena: in std_logic;
	wea: in std_logic_vector(0 downto 0);
	addra: in std_logic_vector(7 downto 0);
	dina: in std_logic_vector(15 downto 0);
	clkb: in std_logic;
	enb: in std_logic;
	addrb: in std_logic_vector(7 downto 0);
	doutb: out std_logic_vector(15 downto 0));
END ram_samples_255x16;
 
ARCHITECTURE ram_samples_255x16_a OF ram_samples_255x16 IS
-- synthesis translate_off
component wrapped_ram_samples_255x16
	port (
	clka: in std_logic;
	ena: in std_logic;
	wea: in std_logic_vector(0 downto 0);
	addra: in std_logic_vector(7 downto 0);
	dina: in std_logic_vector(15 downto 0);
	clkb: in std_logic;
	enb: in std_logic;
	addrb: in std_logic_vector(7 downto 0);
	doutb: out std_logic_vector(15 downto 0));
end component;
 
-- Configuration specification 
	for all : wrapped_ram_samples_255x16 use entity XilinxCoreLib.blk_mem_gen_v4_3(behavioral)
		generic map(
			c_has_regceb => 0,
			c_has_regcea => 0,
			c_mem_type => 1,
			c_rstram_b => 0,
			c_rstram_a => 0,
			c_has_injecterr => 0,
			c_rst_type => "SYNC",
			c_prim_type => 1,
			c_read_width_b => 16,
			c_initb_val => "0",
			c_family => "spartan3",
			c_read_width_a => 16,
			c_disable_warn_bhv_coll => 0,
			c_use_softecc => 0,
			c_write_mode_b => "WRITE_FIRST",
			c_init_file_name => "no_coe_file_loaded",
			c_write_mode_a => "WRITE_FIRST",
			c_mux_pipeline_stages => 0,
			c_has_softecc_output_regs_b => 0,
			c_has_mem_output_regs_b => 0,
			c_has_mem_output_regs_a => 0,
			c_load_init_file => 0,
			c_xdevicefamily => "spartan3a",
			c_write_depth_b => 255,
			c_write_depth_a => 255,
			c_has_rstb => 0,
			c_has_rsta => 0,
			c_has_mux_output_regs_b => 0,
			c_inita_val => "0",
			c_has_mux_output_regs_a => 0,
			c_addra_width => 8,
			c_has_softecc_input_regs_a => 0,
			c_addrb_width => 8,
			c_default_data => "0",
			c_use_ecc => 0,
			c_algorithm => 1,
			c_disable_warn_bhv_range => 0,
			c_write_width_b => 16,
			c_write_width_a => 16,
			c_read_depth_b => 255,
			c_read_depth_a => 255,
			c_byte_size => 9,
			c_sim_collision_check => "ALL",
			c_common_clk => 0,
			c_wea_width => 1,
			c_has_enb => 1,
			c_web_width => 1,
			c_has_ena => 1,
			c_use_byte_web => 0,
			c_use_byte_wea => 0,
			c_rst_priority_b => "CE",
			c_rst_priority_a => "CE",
			c_use_default_data => 0);
-- synthesis translate_on
BEGIN
-- synthesis translate_off
U0 : wrapped_ram_samples_255x16
		port map (
			clka => clka,
			ena => ena,
			wea => wea,
			addra => addra,
			dina => dina,
			clkb => clkb,
			enb => enb,
			addrb => addrb,
			doutb => doutb);
-- synthesis translate_on
 
END ram_samples_255x16_a;