library ieee;

use ieee.std_logic_1164.all;

 

entity toplevel is
	port (
		CLK : in std_logic;
		RST : in std_logic;
		SIGNAL_IN : in std_logic_vector(30 downto 0);
		PARITY : out std_logic
	);

end entity toplevel;

 

architecture RTL of toplevel is

 

component parity_ent
	generic(LENGTH_g : natural := 32);
	port(CLK       : in  std_logic;
		 SIGNAL_IN : in  std_logic_vector(LENGTH_g – 1 downto 0);
		 PARITY    : out std_logic);

end component parity_ent;

 

begin
	parity_inst : component parity_ent
		generic map(LENGTH_g => SIGNAL_IN'length)
		port map(CLK       => CLK,
			     SIGNAL_IN => SIGNAL_IN,
			     PARITY    => PARITY);

 

end architecture RTL;

library ieee;

use ieee.std_logic_1164.all;

 

entity parity_ent is
	generic (
		LENGTH_g : natural := 32
	);
	port (
		CLK : in std_logic;
		SIGNAL_IN : in std_logic_vector(LENGTH_g – 1 downto 0);
		PARITY : out std_logic
	);

end entity parity_ent;

 

architecture RTL of parity_ent is

 

begin

 
			lower_part: for i in 0 to LENGTH_g / 2 – 1 generate
			lower_part_ent: entity work.parity_ent(RTL)
				generic map(LENGTH_g => LENGTH_g / 2)
				port map(CLK => CLK, SIGNAL_IN => SIGNAL_IN, PARITY => PARITY);
			end generate;
			upper_part: for i in LENGTH_g / 2 to LENGTH_g – 1 generate
				upper_part_ent: entity work.parity_ent(RTL)
				generic map (LENGTH_g => LENGTH_g / 2 + (LENGTH_g rem 2))
				port map(CLK => CLK, SIGNAL_IN => SIGNAL_IN, PARITY => PARITY);
			end generate;

 

end architecture RTL;

library ieee;

use ieee.std_logic_1164.all;

 

entity parity_single is
	generic (
		LENGTH_g : natural := 32
	);
	port (
		CLK : in std_logic;
		SIGNAL_IN : in std_logic_vector(LENGTH_g – 1 downto 0);
		PARITY : out std_logic
	);

end entity parity_single;

 

architecture RTL of parity_single is

 

begin
	parity_prcs:process (CLK) is
	begin
		if rising_edge(CLK) then
			if (1 = LENGTH_g) then
			PARITY <= SIGNAL_IN(0);
			elsif (2 = LENGTH_g) then
			PARITY <= SIGNAL_IN(0) xor SIGNAL_IN(1);
			end if;
		end if;
	end process parity_prcs;

 

end architecture RTL;