signal a : std_logic;
signal boo : std_logic;
begin
 
p_something : process(clk) is
    variable foo : std_logic;
    variable barbar : std_logic;
begin
    if rising_edge(clk) then
       -- This block can be aligned with Ctrl-Shift-a
       case whateva is
       when 0 =>
       a <= '1';
       boo <= '0';
 
       when 1 =>
       -- OK
       foo := '0';
       barbar := '1';
 
       when others =>
       -- Not OK
       a <= '1';
       boo <= '0';
       foo := '0';
       barbar := '1';
    end case;
    end if;
end process p_something;