Clocked process not recognised for array
It looks like the clock is not recognised if it is part of an array:
in_ps: for i in 1 to NUMBER_OF_PORTS generate in_page_sw : process(i_reset, i_in_clk(i)) begin if i_reset = '1' then in_page(i) <= '0'; elsif i_in_clk(i)'event and i_in_clk(i) = '1' then if i_page_sw(i) = '1' then in_page(i) <= not in_page(i); end if; end if; end process in_page_sw; end generate in_ps;
Sigasi now reports missing signals in sensitivity list.
Bug or feature?
Regards,
Kurt.
- Forums:
ticket:812
Thanks for the clear VHDL code snippet. I have logged this as ticket:812
Hendrik.
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