compilation error
I don't know if this is ther right place for this kind of question, but I'm just playing around a bit with the HDT environment (trying it out on a rather complex project).
I have a source file that contains:
-- #line
as first line in the file. This gives me the following error
Multiple markers at this line
- mismatched input '<178>' expecting DESIGN_FILE
- 846 changed lines
Don't quite understand why this is ... should be just ignored as it is comment
- Forums:
Syntax error
This is indeed not the best error message. Apparently our parser failed on your file. In that case there is an error marker on the first line. This does not mean the error is on the first line; it just means our parser got lost.
Could you check the log and send it to support@sigasi.com ? Probably an exception occurred.
Fixed
In the next release, there will no longer be a strange error message on the first line of an incorrect file. (was ticket:591)
NoViableAltException
Hello,
I had an invalid not-yet-declared signal name
_LineNumberin my file resulting in :NoViableAltException('_'@[1:1: Tokens : ( ACCESS | AFTER | ALIAS | ALL | ... | STRING_LITERAL | WHITESPACE );]) ICAMHdTx.vhd /ICAMHdTx Unknown HDL problem marker
The invalid name was flagged by the Quartus compiler, after dcalring a proper name the error was gone.
Best regards,
Josy
lexer
Hi Josy,
In our current analyzer (in the lexer, actually) we do not allow names that begin with an underscore, which is what the VHDL standard requires. This results in the illegible error message you saw.
In our next release, the lexer will allow such names, and you get a sensible error message, indicating that the name
_LineNumberis not legal VHDL identifier.Philippe
Lexer
Hi Philippe,
it was not so much the long error message, but the fact that it didn't give the line number where it happened that made me add it to the post.
Best regards,
Josy
line numbers
Point taken. The new version will also indicate line numbers.
Philippe
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