entity show is
    generic (
        g : integer := 1);
    port (
        clk, reset : in std_logic;
        a,b : in std_logic;
        c : out std_logic);
end entity show;

<company header>
library ieee;
use ieee.std_logic_1164.all;
 
entity tb_show is
end entity tb_show;
architecture test of tb_show is
    -- component generics
    constant g : integer := 1;
    -- component ports
    signal clk, reset : std_logic;
    signal a, b       : std_logic;
    signal c          : std_logic;
  -- clock
  signal Clk : std_logic := '1';
  -- finished?
  signal finished : std_logic;
begin  -- architecture test
    -- component instantiation
    DUT: entity work.show
        generic map (
            g => g)
        port map (
            clk   => clk,
            reset => reset,
            a     => a,
            b     => b,
            c     => c);
  -- clock generation
  Clk <= not Clk after 10 ns when finished /= '1' else '0';
  -- waveform generation
  WaveGen_Proc: process
  begin
    finished <= '0';
      -- insert signal assignments here
    finished <= '1';
    report (time'image(now) & " Finished");
    wait;
  end process WaveGen_Proc;
end architecture test;
--------------------------------------------------------------------------
configuration tb_show_test_cfg of tb_show is
    for test
    end for;
end tb_show_test_cfg;
--------------------------------------------------------------------------

(custom-set-variables
 '(vhdl-clock-edge-condition (quote function))
 '(vhdl-company-name "TRW Limited")
 '(vhdl-directive-keywords (quote ("pragma" "synopsys" "synthesis")))
 '(vhdl-end-comment-column 130)
 '(vhdl-file-header "-- balh, copyright etc.
<cursor>
")
 '(vhdl-reset-kind (quote none))
 '(vhdl-standard (quote (93 nil)))
 '(vhdl-testbench-declarations "  -- clock
  signal Clk : std_logic := '1';
  -- finished?
  signal finished : std_logic;
")
 '(vhdl-testbench-directory-prefix "./")
 '(vhdl-testbench-entity-name (quote (".*" . "tb_\\&")))
 '(vhdl-testbench-statements "  -- clock generation
  Clk <= not Clk after 10 ns when finished /= '1' else '0';
 
  -- waveform generation
  WaveGen_Proc: process
  begin
    finished <= '0';
      -- insert signal assignments here
    finished <= '1';
    report (time'image(now) & \" Finished\");
    wait;
  end process WaveGen_Proc;
")