enhancement to the align feature

Posted Tue, 2011-05-24 20:16 by ndhuffma

I'd like to request an enhancement to the align feature for port declarations.

If I have a port declaration that looks like this:

  ctrl_master_read        : out   std_logic;
  ctrl_master_address     : out   std_logic_vector(31 downto 0);
  ctrl_master_readdata    : in    std_logic_vector(31 downto 0);
  ctrl_master_waitrequest : in    std_logic;
 
  exp_slave_read : in    std_logic;
  exp_slave_write : in std_logic;
  exp_slave_readdata : out std_logic_vector(31 downto 0);
  exp_slave_writedata : out std_logic_vector(31 downto 0);
  exp_slave_address : in    std_logic_vector(7 downto 0);

and use the sigasi align functionality I get this:
  ctrl_master_read        : out   std_logic;
  ctrl_master_address     : out   std_logic_vector(31 downto 0);
  ctrl_master_readdata    : in    std_logic_vector(31 downto 0);
  ctrl_master_waitrequest : in    std_logic;
 
  exp_slave_read          : in    std_logic;
  exp_slave_write         : in std_logic;
  exp_slave_readdata      : out std_logic_vector(31 downto 0);
  exp_slave_writedata     : out std_logic_vector(31 downto 0);
  exp_slave_address       : in    std_logic_vector(7 downto 0);

but what I really want is this:
  ctrl_master_read        : out   std_logic;
  ctrl_master_address     : out   std_logic_vector(31 downto 0);
  ctrl_master_readdata    : in    std_logic_vector(31 downto 0);
  ctrl_master_waitrequest : in    std_logic;
 
  exp_slave_read          : in    std_logic;
  exp_slave_write         : in    std_logic;
  exp_slave_readdata      : out   std_logic_vector(31 downto 0);
  exp_slave_writedata     : out   std_logic_vector(31 downto 0);
  exp_slave_address       : in    std_logic_vector(7 downto 0);

with all of the types aligned as well as it looks a bit more clean.

‹ Xilinx Webpack 12.1, linux 64 bits Manual Update of Eclipse Plugin ›

Hi Nathanael, We have a

by philippe.faes (Sigasi) - 2011-05-26 08:13

Hi Nathanael,
We have a better aligner in the HDT 2.0 tech preview. The extra whitespace will be eliminated, so your code will look less messy. At this time, however, we do not align the data types:

  ctrl_master_read        : out std_logic;
  ctrl_master_address     : out std_logic_vector(31 downto 0);
  ctrl_master_readdata    : in std_logic_vector(31 downto 0);
  ctrl_master_waitrequest : in std_logic;
 
  exp_slave_read          : in std_logic;
  exp_slave_write         : in std_logic;
  exp_slave_readdata      : out std_logic_vector(31 downto 0);
  exp_slave_writedata     : out std_logic_vector(31 downto 0);
  exp_slave_address       : in std_logic_vector(7 downto 0);

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