library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
 
entity testme_2 is
	generic (
		NUM_OF_CHAN			  	 : integer := 1	);
	port (
		Clk	        : in std_logic;
		Enable	  	: out std_logic_vector(NUM_OF_CHAN downto 0)
		);	
end entity testme_2;
 
 
architecture rtl_1 of testme_2 is
	signal channelCnt : unsigned(1 downto 0);
 
	function setColorNextPix(index : in unsigned) return unsigned is
		variable nextIndex : unsigned(index'length-1 downto 0);
	begin
		if index < NUM_OF_CHAN - 1 then
			nextIndex := index + 1;
		else
			nextIndex := (others => '0');
		end if;
		return nextIndex;
	end function setColorNextPix;
begin
	process(Clk)
	begin
		if rising_edge(Clk) then
				Enable(to_integer(setColorNextPix(channelCnt) + 1)) <= '1';
		end if;
	end process;
end architecture rtl_1;