Hi,

Following the tutorial (VHDL, Starter version of the tool, version 2.2), I was at the last stage and added a new line of code in the counter process (dut.vhd) after the if reset = '1' then statement: this new line of code was: new_signal_s <= true;

At that time, new_signal_s had not been declared and, as a result, it was correctly detected as a problem by the editor.
I then went to the declarative region of the architecture and wrote the following signal declaration:
signal new_signal_s : std_logic;
No error markers appeared anywhere, even after I saved the file.

I then tried a 2nd experiment: I declared a new type: type deleteme_t is (value1, value2);
After that, I added another statement in the counter process again (below the statement mentioned above) as follows:
new_signal2_s <= value3;

An error marker appeared at that point.
I then added the following signal declaration: signal new_signal2_s : boolean;
An error marker remained at the line where the statement new_signal2_s <= value3; appeared in the code; the 'explanation' of the error marker (when hovering over it) was: "Could not find declaration corresponding to 'value3'".

In conclusion, it appears that when the declaration of a signal is done after the signal has already been used in an assignment, there is no checking between the type in the declaration and that in the assignment.
Is this check not intended to be performed by the tool? Or is it a limitation of the Starter Edition?
(at least in the case of new_signal2_s it seemed to detect that value3 was not a declared value)

Any clarification would be welcome.
Thanks