config_done_irq_prcs:process (csi_CLK_clock) is
		signal config_done_int_reg : std_logic := '0';
	begin
		if rising_edge(csi_CLK_clock) then
		config_done_int_reg <= config_done_int;
			if  '1' = config_done_int and '0' = config_done_int_reg then
			config_done_irq <= '1';
			elsif '1' = avs_CONFIG_DONE_IRQ_ACK_write then
				config_done_irq <= '0';
			end if;
		end if;
	end process config_done_irq_prcs;