Format does not seem to deal with alias declarations correctly

Posted Wed, 2012-01-04 17:06 by ndhuffma

This is just a formatting nitpick, but I use alias definitions in some places and usually define them immediately below the signal declaration with which they're associated. When I use the Format (Ctrl+Shift+F) to align my various declarations and it appears that alias definitions are not ignored (as the white-space is modified) but aren't properly aligned either.

signal test_sig1_long_name : std_logic;

signal test_sig2 : std_logic;

signal test_sig3           : std_logic_vector(2 downto 0);

alias test_alias1   : std_logic is test_sig3(0);

alias test_alias2      : std_logic_vector(1 downto 0) is test_sig3(2 downto 1);

signal test_sig4 : std_logic_vector(2 downto 0);

formats to this: 
signal test_sig1_long_name : std_logic;

signal test_sig2           : std_logic;

signal test_sig3           : std_logic_vector(2 downto 0);

alias test_alias1 : std_logic is test_sig3(0);

alias test_alias2 : std_logic_vector(1 downto 0) is test_sig3(2 downto 1);

signal test_sig4 : std_logic_vector(2 downto 0);
rather than this which is what I would have expected (and what I'd like): 
signal test_sig1_long_name : std_logic;

signal test_sig2           : std_logic;

signal test_sig3           : std_logic_vector(2 downto 0);

alias test_alias1          : std_logic is test_sig3(0);

alias test_alias2          : std_logic_vector(1 downto 0) is test_sig3(2 downto 1);

signal test_sig4           : std_logic_vector(2 downto 0);

‹ VHDL-2008: support for nested generate statements protected types ›

You sure have a point. Logged

by philippe.faes (Sigasi) - 2012-01-05 08:55

You sure have a point. Logged as ticket:1883.

Post new comment

The content of this field is kept private and will not be shown publicly.
By submitting this form, you accept the Mollom privacy policy.