Functions and procedures in outline view

Posted Mon, 2010-12-06 15:40 by StMartin81_2

Is there a way to show functions and procedures of a vhdl file in outline view (or somewhere else)? If not this would be a very much appreciated feature for sigasi.

Martin

‹ "Add Port" Action Create File Template ›

Outline

by heeckhau (Sigasi) - 2010-12-06 18:35

Hi Martin,

where are you missing subprograms in the outline? We currently already display them in the declarative part of packages, architectures, ...

Hendrik.

I am using a testbench where

by StMartin81_2 - 2010-12-07 14:09

I am using a testbench where I use functions and procedures inside the architecture and the subprograms are not shown in the outline view, for example:

architecture...
begin
procedure xyz
is begin
...
end procedure xyz;
...
end architecture ...

Subprograms in outline

by heeckhau (Sigasi) - 2010-12-07 15:00

Functions an procedures should be visible in the outline view. They are grouped in a Declarations section.

Subprograms in outlineSubprograms in outline

Subprograms in outline: It

by StMartin81_2 - 2010-12-07 16:28

Subprograms in outline: It doesn't seem to work for me.Subprograms in outline: It doesn't seem to work for me.

Hmm

by philippe.faes (Sigasi) - 2010-12-07 16:42

Hmm, that's interesting. Could you send me this file (or a trimmed-down file) so that we can reproduce this problem?

Thanks.

The procedures are defined

by StMartin81_2 - 2010-12-08 10:22

The procedures are defined inside a process. Perhaps that could be the source of the problem?

Processes

by heeckhau (Sigasi) - 2010-12-08 10:37

Hi Martin,

we indeed do not show declarations and statements in a process in the outline view. I have logged your feature request as ticket:1072

Hendrik.

+1

by ricardo - 2011-04-14 19:03

I would like to second that. This is particularly important specially when coding testbenches, if you follow the approach described by Janick Bergeron in 'Writing Testbenches - Functional Verification of HDL Models'.

entity bit_matrix_tb is
end entity bit_matrix_tb;
 
architecture testbench of bit_matrix_tb is begin
 
  run_test_cases: process is 
 
    procedure test_null_bit_matrix is begin
      ...
    end procedure;
 
    procedure test_identity_bit_matrix is begin
      ...
    end procedure;
 
    procedure test_matrix_column is begin
      ...
    end procedure;
 
    procedure test_matrix_row is begin
      ...
    end procedure;
 
    procedure test_exchange_rows is begin
      ...
    end procedure;
 
  begin
    puts("Testing package bit_matrix");
 
    test_null_bit_matrix;
    test_identity_bit_matrix;
    test_matrix_column;
    test_matrix_row;
    test_exchange_rows;
 
    puts("All tests ran ok.");
    wait;
  end process;
 
end architecture testbench;

Thanks for your input. Note

by philippe.faes (Sigasi) - 2011-04-14 20:35

Thanks for your input.

Note that you can usually put the procedure declarations in the declarative part of the architecture as well.

Thanks for pointing it out

by ricardo - 2011-04-14 21:57

Thanks for pointing it out; indeed, I could not recall why I had declared those procedures inside the process. However, when I tried to move them up to the architecture, Modelsim reminded me of the reason:

-- Compiling entity b4_candidate_codeword_generation_tb
-- Compiling architecture testbench of b4_candidate_codeword_generation_tb
** Error: vhdl/testbench/b4_candidate_codeword_generation_tb.vhd(38): Cannot drive signal "clock" from procedure "pulse_clock".
** Error: vhdl/testbench/b4_candidate_codeword_generation_tb.vhd(40): Cannot drive signal "clock" from procedure "pulse_clock".
** Error: vhdl/testbench/b4_candidate_codeword_generation_tb.vhd(45): Cannot drive signal "rwa" from procedure "reset_with_default_inputs".
** Error: vhdl/testbench/b4_candidate_codeword_generation_tb.vhd(46): Cannot drive signal "ui" from procedure "reset_with_default_inputs".
** Error: vhdl/testbench/b4_candidate_codeword_generation_tb.vhd(47): Cannot drive signal "gr" from procedure "reset_with_default_inputs".
** Error: vhdl/testbench/b4_candidate_codeword_generation_tb.vhd(48): Cannot drive signal "psi" from procedure "reset_with_default_inputs".
** Error: vhdl/testbench/b4_candidate_codeword_generation_tb.vhd(49): Cannot drive signal "b4_input_ready" from procedure "reset_with_default_inputs".
** Error: vhdl/testbench/b4_candidate_codeword_generation_tb.vhd(50): Cannot drive signal "b4_output_request" from procedure "reset_with_default_inputs".
** Error: vhdl/testbench/b4_candidate_codeword_generation_tb.vhd(52): Cannot drive signal "reset" from procedure "reset_with_default_inputs".
** Error: vhdl/testbench/b4_candidate_codeword_generation_tb.vhd(88): Cannot drive signal "ui" from procedure "test_with_simplest_inputs".
** Error: vhdl/testbench/b4_candidate_codeword_generation_tb.vhd(89): Cannot drive signal "psi" from procedure "test_with_simplest_inputs".
** Error: vhdl/testbench/b4_candidate_codeword_generation_tb.vhd(90): Cannot drive signal "reset" from procedure "test_with_simplest_inputs".

Simply put, if I choose to declare the process within the architecture, I must pass a multitude of signals as parameters, which might not be practical in the case of a testbench.

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