In your documentation and tutorials you also speak about "design hierarchy". Normally the design is composed by multiple modules and I was expecting to see a real full design hierarchy where I have the top modules and then the other ones organized in a tree view.
I understand that once you open the file containing the top module you really have the full design hierachy, but once you navigate opening an inner module you loose that view, and the only way to go back is to click again in the tab containing the top module. It is extremaly frustrating if you need to browse inside a big project (with about 90 modules) not written by you...
It seems that the editor has only a file/module view and not a real design view... It should be useful to have the ability to lock the hierachy view to one file that should be designated as the top module so that it always reflect the entire design hierarchy.
I have seen a small undocumented triangle in the hierachy view that says "Select toplevel..." but the result I obtain is to loose the control of the view and have it empty once I change focus to another tab.

Another useful option should be to have also a filter in the hierarchycal view where we can hide objects like signals and processed and also the option to have a flat a-z ordered view where it easy to locate something inside of the entire design.

I have also found the "rename" feature extremely slow, considering a project with only 9 files! It took about 30 seconds before showing the preview window... I agree that it is anyway faster than manualy changing all the references, but I uses other refactor tool inside Visual Studio that are 100 time faster...

Also a last comment about port management in the entity. It seems to me that it is not possible to remove ports but only to add, and once you add it is added only at the end of the module... Not to say what it happens to the formatting...

Thank you anyway for having build an useful tool for writing VHDL...