Hi sigasi team,

I encountered a situation where Sigasi HDT seems to report an "Unused declaration" even if the signal concerned is used within a port map.

A VHDL-file with the following contents gives "Unused declaration" warning:

library ieee;
use ieee.std_logic_1164.all;
 
entity testme is
port (
	out_a : out std_logic_vector(1 downto 0)
);
end testme;
 
 
library ieee;
use ieee.std_logic_1164.all;
 
entity testme_1 is
end testme_1;
 
architecture RTL of testme_1 is
	signal test1 : std_logic;
	signal test2 : std_logic;
 
begin
	topd_0 : entity work.testme
	port map (
	out_a(0) => test1,
	out_a(1) => test2
	);
end architecture RTL;

Warning is thrown for signal "test1" only.
test2 is not affected.
May be there is an issue when port names occur twice within a port map!?

EDIT: added a simpler example (which actually compiles corectly)

Regards,
Josef