Outline for files not belonging to any project

It would be nice if outline would also work for vhdl files that do not belong to the current project. If I want to have a quick look at a file, I currently only get syntax highlighting. Having the outline of the file available for easy navigation would be great.

Outlines and (limited) error

Outlines and (limited) error markers in isolated VHDL files will be supported in the 2.0 version of our product. There is currently a technology preview available: http://www.sigasi.com/sigasi-hdt-2.0-preview

To clarify: the tech preview

To clarify: the tech preview that is currently available for download does not yet support editing, outline and error checking for isolated files. We hope to get this ready in one of the upcoming releases.

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