library ieee;

use ieee.std_logic_1164.all;

use ieee.numeric_std.all;

entity testtop is

end entity;

architecture tb of testtop is

signal clk      : std_logic;

signal reset    : std_logic;

signal output   : std_logic;

begin

DUT: entity work.test_bottom

port map (
    clk     => clk,
    reset   => reset,  
    output  => output

);

end tb;

library ieee;

use ieee.std_logic_1164.all;

use ieee.numeric_std.all;

entity test_bottom is

port (
    clk     : in    std_logic;
    reset   : in    std_logic;
   -- test_input    : in    std_logic;   --UNCOMMENT THIS LINE
    output  : out   std_logic

);

end entity;

architecture rtl of test_bottom is

begin

output  <= '0';             --COMMENT OUT THIS LINE

--output  <= test_input;    --UNCOMMENT THIS LINE

end; 

 library ieee;

use ieee.std_logic_1164.all;

use ieee.numeric_std.all;

entity test_bottom is

port (
    clk     : in    std_logic;
    reset   : in    std_logic;
    test_input    : in    std_logic;   --UNCOMMENT THIS LINE
    output  : out   std_logic

);

end entity;

architecture rtl of test_bottom is

begin

--output  <= '0';             --COMMENT OUT THIS LINE

output  <= test_input;    --UNCOMMENT THIS LINE

end; 

library ieee;

use ieee.std_logic_1164.all;

use ieee.numeric_std.all;

entity testtop is

end entity;

architecture tb of testtop is

signal clk      : std_logic;

signal reset    : std_logic;

signal output   : std_logic;

begin

DUT: entity work.test_bottom

port map (
    clk     => clk,
    reset   => reset,  
    test  => output   --Problem is here, test is a new port, now we're missing output and test is incorrectly assigned and no errors are flagged.  This should leave output alone and flag an error that input test is missing (which is flagged pre-rename)

);

end tb;