Quickfix and types

Posted Tue, 2010-04-27 08:39 by trondd

Problem: 

architecture RTL of foo
    signal reg : std_logic_vector(15 downto 0);
begin
    p_bar : process(clk, reset) is
    begin
        if rising_edge(clk) then
            my_port <= reg(reg'high); -- Note: Missing signal declaration.
        end if;
    end process p_bar;
end architecture RTL;

Now try to quickfix the problem listed in the code.

Result: 

architecture RTL of foo
    signal reg : std_logic_vector(15 downto 0);
    signal my_port : std_logic_vector(15 downto 0);
begin
    p_bar : process(clk, reset) is
    begin
        if rising_edge(clk) then
            my_port <= reg(reg'high);
        end if;
    end process p_bar;
end architecture RTL;

my_port was created with the type of reg, and not the type of the slice, which in this case is std_logic.

‹ Rename of Type element unused declaration ›

Heuristics

by heeckhau (Sigasi) - 2010-04-27 13:24

Hi Trond,

the 'generate signal declaration' quickfix is currently based on heuristics and indeed not always correct (see also this issue).
I have logged this as ticket:793.

Kind regards,
Hendrik.

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