library ieee;
use ieee.std_logic_1164.all;
 
entity testme0 is
end testme0;
 
architecture rtl0 of testme0 is
 
	signal test_sig : std_logic_vector(7 downto 0);
 
	alias slice0 : std_logic_vector(3 downto 0) is test_sig(7 downto 4);
	alias slice1 : std_logic_vector(3 downto 0) is test_sig(3 downto 0);
 
begin
	test_sig(1 downto 0) <= "11";
	slice0(1 downto 0) <= "11"; -- throws RecognitionException
 
end architecture rtl0;