Sigasi 2.0: Assignments of std_logic to std_logic_vector

Posted Thu, 2011-10-06 16:51 by StMartin81_2

It would be nice to have a feature which produces a warning when trying to do the follwing:

signal my_vec : std_logic_vector (3 downto 0);
signal my_sig : std_logic;
…
my_sig <= my_vec;

my_vec <= my_sig;

Best regards
Martin

by philippe.faes (Sigasi) - 2011-10-06 17:41

Hi Martin, just like in Sigasi 1.0, we don't have a type checking system (yet). Thanks for bringing this up though, it helps us set our priorities.

-- Philippe

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