Sigasi HDT does not raise any error or warning when reading from an output port
I would expect this to be flagged as an error:
entity foo is port ( clk : in std_logic; -- Note output port! boo : out std_logic ); end entity foo; architecture RTL of foo is signal my_reg : std_logic; begin -- This should yield an error or at least a warning. my_reg <= boo; end architecture RTL;
Some tools will convert this to a buffer automatically, but I do not think it is recommended coding style.
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Correct: feature request
Hi Trond,
You are right that this code is incorrect. Thanks for posting the example.
We do not strive to mark all errors and problems. Instead we strive to provide quick feedback and mark only the most common errors.
Having said that, I agree that this is one we should catch. I have created a ticket for this (ticket:763).
Philippe
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