Support for autocompletion of constant signals

Posted Wed, 2012-01-25 12:55 by StMartin81_2

Hello,

it would be nice to have auto completion support for constant signals also.

Also auto completion for states would be great:

type state_t is (POWER_UP_s, RESET_s, CONFIG_s, FINISHED_s);

signal my_sig : state_t := POWER_UP_s;

….

my_sig <= RES<auto completion here>

Regards
Martin

‹ Add error marker for: Range expression must not be in parentheses. Can't create new VHDL file ›

ticket:1894

by heeckhau (Sigasi) - 2012-01-26 09:03

Hi Martin,

The autocomplete should indeed be improved in this case. I have logged this as ticket:1894
As a workaround you can use Eclipse's Word Completion (Alt+/) instead of the VHDL specific autocomplete. This is a dictionary based autocomplete similar to what Emacs and VI offer.

Kind regards,
Hendrik.

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