using libraries other than work

Can I set the library that a given file is compiled into?

libraries

Yes, you can choose your libraries in the project properties. For more info check the Manual's chapter on VHDL Libraries: Help > Help Contents > Sigasi HDT > Sigasi HDT User Manual > VHDL Libraries.

Philippe

VHDL Libraries

I am still having difficulty in setting the libraries for my project. The project explorer does not reflect in which library my components exist. At present the explorer states that they are all in "work".

How do we correct this, I have tried the library mapping method but it does not seem to work. My libraries reside in a directory

ProjectName->Library->A_Lib
ProjectName->Library->B_Lib
:
:
ProjectName->Library->Z_Lib

and the packages

ProjectName->Packages->A_pkg
ProjectName->Packages->B_pkg
:
:
ProjectName->Packages->Z_pkg

And my components

ProjectName->Component_1->Source->VHDL_1
ProjectName->Component_2->Source->VHDL_2
ProjectName->Component_3->Source->VHDL_3

which are then belong to and compiled for arguments sake into
ProjectName->Packages->A_pkg
ProjectName->Library->A_Lib

and so on.

Regards
Guy

.libraries.xml file

Hi Guy,

there is probably something wrong with your library configuration.

Press Shift-Ctrl-R and type .libraries.xml and add the contents as a reply. Then I will look into your problem.

Hendrik.

I wondered if you could do it

I wondered if you could do it in a similar way to Synplify. When you highlight the file and right click it allows you to select the library associated with that component.

Regards
Guy

.libraries.xml

<?xml version="1.0" encoding="UTF-8"?>
<libraryMapper>
    <version>1</version>
    <item
        excluding="/backend|/backend/_primary.dat|/backend/_primary.dbs|/backend/rtl.dat|/backend/rtl.dbs|/backend/rtl.prw|/backend/rtl.psm|/components|/components/_primary.dat|/components/_primary.dbs|/components/_vhdl.prw|/components/_vhdl.psm|/core1553_top|/core1553_top/_primary.dat|/core1553_top/_primary.dbs|/core1553_top/def_arch.dat|/core1553_top/def_arch.dbs|/core1553_top/def_arch.prw|/core1553_top/def_arch.psm|/core1553brt|/core1553brt/_primary.dat|/core1553brt/_primary.dbs|/core1553brt/rtl.dat|/core1553brt/rtl.dbs|/core1553brt/rtl.prw|/core1553brt/rtl.psm|/cwlegality|/cwlegality/_primary.dat|/cwlegality/_primary.dbs|/cwlegality/rtl.dat|/cwlegality/rtl.dbs|/cwlegality/rtl.prw|/decoder|/decoder/_primary.dat|/decoder/_primary.dbs|/decoder/rtl.dat|/decoder/rtl.dbs|/decoder/rtl.prw|/decoder/rtl.psm|/encoder|/encoder/_primary.dat|/encoder/_primary.dbs|/encoder/rtl.dat|/encoder/rtl.dbs|/encoder/rtl.prw|/encoder/rtl.psm|/rt1553b|/rt1553b/_primary.dat|/rt1553b/_primary.dbs|/rt1553b/rtl.dat|/rt1553b/rtl.dbs|/rt1553b/rtl.prw|/rt1553b/rtl.psm|/rtcomps|/rtcomps/_primary.dat|/rtcomps/_primary.dbs|/rtcomps/_vhdl.prw|/rtcomps/_vhdl.psm"
        library="core1553brt_lib" location="project:/Library/core1553brt_lib"/>
    <item library="std" location="resource:/com/sigasi/vhdl/std"/>
    <item library="ieee" location="resource:/com/sigasi/vhdl/ieee"/>
    <item library="ieee" location="resource:/com/sigasi/vhdl/vital2000"/>
    <item
        excluding="/rx_control_logic/VHDL_Source/Archive|/synthesiser/VHDL_Source/Archive"
        library="work" location="project:/"/>
    <item library="ModelSim_Lib" location="file:/C:/Actel/Libero_v8.6/Model/modelsim_lib/util"/>
    <item
        excluding="/_info|/_temp|/_temp/vlog0h91js|/_temp/vlog2t8qqr|/_temp/vlog4ssq7f|/_temp/vlog4zvyvg|/_temp/vlog6eq007|/_temp/vlog82448x|/_temp/vlog8gi104|/_temp/vlogdm2fq9|/_temp/vlogenbe39|/_temp/vloggr74s6|/_temp/vlogm06mv8|/_temp/vlogqswtjd|/_temp/vlogt493b4|/_temp/vlogwxeyf6|/_vmake|/alphasat_pkg/_primary.dat|/alphasat_pkg/_primary.dbs|/alphasat_pkg/_vhdl.prw|/alphasat_pkg/body.dat|/alphasat_pkg/body.dbs|/alphasat_pkg/body.prw|/clk_divider|/clk_divider/_primary.dat|/clk_divider/_primary.dbs|/clk_divider/rtl.dat|/clk_divider/rtl.dbs|/clk_divider/rtl.prw|/clock_20mhz|/clock_20mhz/_primary.dat|/clock_20mhz/_primary.dbs|/clock_20mhz/def_arch.dat|/clock_20mhz/def_arch.dbs|/clock_20mhz/def_arch.prw|/clock_20mhz/def_arch.psm|/core1553_top|/core1553_top/_primary.dat|/core1553_top/_primary.dbs|/core1553_top/def_arch.dat|/core1553_top/def_arch.dbs|/core1553_top/def_arch.prw|/data_controller|/data_controller/_primary.dat|/data_controller/_primary.dbs|/data_controller/rtl.dat|/data_controller/rtl.dbs|/data_controller/rtl.prw|/detector_ctrl|/detector_ctrl/_primary.dat|/detector_ctrl/_primary.dbs|/detector_ctrl/rtl.dat|/detector_ctrl/rtl.dbs|/detector_ctrl/rtl.prw|/detector_ctrl/rtl.psm|/detector_dem|/detector_dem/_primary.dat|/detector_dem/_primary.dbs|/detector_dem/rtl.dat|/detector_dem/rtl.dbs|/detector_dem/rtl.prw|/detector_dem/rtl.psm|/detector_int|/detector_int/_primary.dat|/detector_int/_primary.dbs|/detector_int/rtl.dat|/detector_int/rtl.dbs|/detector_int/rtl.prw|/detector_int/rtl.psm|/detector_pkg|/detector_pkg/_primary.dat|/detector_pkg/_primary.dbs|/detector_pkg/_vhdl.prw|/detector_pkg/_vhdl.psm|/detector_sat|/detector_sat/_primary.dat|/detector_sat/_primary.dbs|/detector_sat/rtl.dat|/detector_sat/rtl.dbs|/detector_sat/rtl.prw|/detector_sat/rtl.psm|/detector_top|/detector_top/_primary.dat|/detector_top/_primary.dbs|/detector_top/rtl.dat|/detector_top/rtl.dbs|/detector_top/rtl.prw|/detector_top/rtl.psm|/detector_wrapper|/detector_wrapper/_primary.dat|/detector_wrapper/_primary.dbs|/detector_wrapper/rtl.dat|/detector_wrapper/rtl.dbs|/detector_wrapper/rtl.prw|/detector_wrapper/rtl.psm|/divider/_primary.dat|/divider/_primary.dbs|/divider/rtl.dat|/divider/rtl.dbs|/divider/rtl.prw|/heartbeat|/heartbeat/_primary.dat|/heartbeat/_primary.dbs|/heartbeat/rtl.dat|/heartbeat/rtl.dbs|/heartbeat/rtl.prw|/heartbeat/rtl.psm|/hlo_synthesiser/_primary.dat|/hlo_synthesiser/_primary.dbs|/hlo_synthesiser/rtl.dat|/hlo_synthesiser/rtl.dbs|/hlo_synthesiser/rtl.prw|/lo_cal_synth/_primary.dat|/lo_cal_synth/_primary.dbs|/lo_cal_synth/rtl.dat|/lo_cal_synth/rtl.dbs|/lo_cal_synth/rtl.prw|/memory_address_pkg/_primary.dat|/memory_address_pkg/_primary.dbs|/memory_address_pkg/_vhdl.prw|/memory_address_pkg/body.dat|/memory_address_pkg/body.dbs|/memory_address_pkg/body.prw|/memory_arbiter/_primary.dat|/memory_arbiter/_primary.dbs|/memory_arbiter/rtl.dat|/memory_arbiter/rtl.dbs|/memory_arbiter/rtl.prw|/pe33632_if/_primary.dat|/pe33632_if/_primary.dbs|/pe33632_if/rtl.dat|/pe33632_if/rtl.dbs|/pe33632_if/rtl.prw|/rx_control_logic/_primary.dat|/rx_control_logic/_primary.dbs|/rx_control_logic/rtl.dat|/rx_control_logic/rtl.dbs|/rx_control_logic/rtl.prw|/synth_control/_primary.dat|/synth_control/_primary.dbs|/synth_control/rtl.dat|/synth_control/rtl.dbs|/synth_control/rtl.prw|/synthesiser/_primary.dat|/synthesiser/_primary.dbs|/synthesiser/rtl.dat|/synthesiser/rtl.dbs|/synthesiser/rtl.prw|/synthesizer_pkg/_primary.dat|/synthesizer_pkg/_primary.dbs|/synthesizer_pkg/_vhdl.prw|/synthesizer_pkg/body.dat|/synthesizer_pkg/body.dbs|/synthesizer_pkg/body.prw|/tb_detector/_primary.dat|/tb_detector/_primary.dbs|/tb_detector/rtl.dat|/tb_detector/rtl.dbs|/tb_detector/rtl.prw|/tx_control_logic/_primary.dat|/tx_control_logic/_primary.dbs|/tx_control_logic/rtl.dat|/tx_control_logic/rtl.dbs|/tx_control_logic/rtl.prw|/unit_simulator/_primary.dat|/unit_simulator/_primary.dbs|/unit_simulator/rtl.dat|/unit_simulator/rtl.dbs|/unit_simulator/rtl.prw"
        library="alphasat_lib" location="project:/Library/alphasat_lib"/>
    <item
        excluding="/alphasat_pkg.vhd|/alphasat_pkg.vhd.bak|/cmd_mode_code_pkg.vhd|/lib_comp.tcl|/memory_address_pkg.vhd|/synthesizer_pkg.vhd|/synthesizer_pkg_091113.vhd|/transcript"
        library="dsp_lib" location="project:/Library/dsp_lib"/>
</libraryMapper>

Hi Guy, I built a small

Hi Guy,

I built a small project that resembles your description. Here are some screenshots that will help you configure your library settings.

Let me know if you need some extra help.

question n286 project explorerquestion n286 project explorer

question n286 libraries editorquestion n286 libraries editor

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