VHDL 2008

Posted Wed, 2011-01-05 18:27 by MSnook

I am aware that there is some discussion going on regarding support of VHDL 2008 features.

What current features are support and what is the roadmap for further features?

How will you deal with syntax that is not yet supported?

Tools such as modelsim and quartus are beginning to offer very good support for these features.

The most notable of which are enhanced generics in packages, the all keyword for processes, unconstrained types, and enhanced case statements.

The tool is great and I hope it can keep up with these new features so that it can be integrated with our flow.

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Hi Mike, Unconstrained arrays

by philippe.faes (Sigasi) - 2011-01-06 17:18

Hi Mike,

Unconstrained arrays work fine today.

"procedure(all)" and "case?" can be done soon.

Generics for packages are more complex. We want to start working on them within the current year (2011) but they require a significant effort.

procedure(all) and case? have

by philippe.faes (Sigasi) - 2011-02-01 21:58

procedure(all) and case? have been released in January 2010

VHDL 2008 Comments

by James (not verified) - 2011-04-13 20:27

Yes, and an additional feature in VHDL 2008 is the "C" style comments made available by:

/*-------------------------
Some example
comments here
end comments
--------------------------*/

I am wondering if this will be supported anytime soon as well.

Thanks,

James

Hi James, there have been a

by philippe.faes (Sigasi) - 2011-04-14 15:51

Hi James, there have been a few requests in a row for this. I'll check if we can squeeze this in.

Released

by philippe.faes (Sigasi) - 2011-05-10 20:39

Hi James, multi-line comments are supported as of today's release.

VHDL 2008 Continued

by jbonanno1 - 2011-04-14 16:39

Phillipe;

Thanks for the feedback. I have been impressed by the Sigasi tool. If it incorporates features of VHDL 2008, it will be even more powerful. One thing about VHDL 2008 is that it reduces the verbosity of the language, making it have some hybrid qualities to Verilog and C, and overall is a significant enhancement. So if Sigasi can support it I think it would be great.

James

Thanks, we're working hard to

by philippe.faes (Sigasi) - 2011-04-14 20:38

Thanks, we're working hard to get there. You may have noticed that we have some VHDL 2008 features implemented. There's still lots to be done, though!

Supported VHDL Features

by James (not verified) - 2011-04-14 20:54

Philippe; Thanks for the features of VHDL 2008 that are supported. The conditional operator

if ??EN then
y <= x;
else
y <= '0';
end if;

is not yet supported?? Albeit that you have it for the case statement . . . .

Thanks, James

implied

by philippe.faes (Sigasi) - 2011-06-18 05:47

Hi James,
The condition operator '??' is implied in the IF statement. That means you don't have to type it, and things would still work. The LRM (IEEE 1076-2008) specifies in section 9.2.9 that:

In certain circumstances, the condition operator is implicitly applied to an expression that occurs as a condition in any of the following places:
— After until in the condition clause of a wait statement (see 10.2)
— After assert in an assertion, either in an assertion statement (see 10.3) or in a concurrent assertion statement (see 11.5)
— After if or elsif in an if statement (see 10.8)
— […]

Conditional Operator

by Jame (not verified) - 2011-06-18 17:31

Okay, the ?? does not need to be explicitly typed according to the LRM, however in synthesis tools such as Altera I had not seen this declaration before. I will attempt to synthesize a design with this type of construct in Quartus and see what happens. The ultimate question is whether the synthesis tool supports this or not. Thanks, James

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