VHDL-2008: support for nested generate statements
Hello,
the following code is valid in VHDL-2008:
assign_top_channel_mask_bits : if 1 < channel_bit_mask_arr'length generate channel_mask(channel_mask'high downto ((channel_bit_mask_arr'length – 1) * channel_mask_data_width_c)) <= channel_bit_mask_arr(channel_bit_mask_arr'length – 1) (max_nr_channels_c – (channel_bit_mask_arr'length – 1) * channel_mask_data_width_c – 1 downto 0);
assign_channel_mask_gen : for i in 0 to channel_bit_mask_arr'length – 2 generate channel_mask((((i + 1) * channel_mask_data_width_c) – 1) downto(i * channel_mask_data_width_c)) <= channel_bit_mask_arr(i); end generate assign_channel_mask_gen;
else generate channel_mask <= channel_bit_mask_arr(0)(channel_mask'range);
end generate assign_top_channel_mask_bits;
It would be nice to see this supported in Sigasi.
Regards
Martin
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VHDL 2008
Thanks for your feedback. Logged as ticket 1888
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