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How to automatically run the ModelSim Makefile in Sigasi HDT?

Sigasi HDT automatically and transparently analyzes your VHDL code in the background while you are designing. Sigasi's objective is to do this as fast as possible to give you real-time feedback. Of course you also still have to simulate your code with a VHDL simulator such as ModelSim. Since a few months, Sigasi HDT can automatically create and update a Makefile to compile your project with ModelSim. And through the use of a builder it is also possible to automatically run this Makefile when you make changes to your design. In this blog post I will explain how.

First verify that vcom and vlib are on your path or add it (export PATH=/opt/altera9.0/modelsim_ase/bin/:$PATH on my machine).

Next make sure that Sigasi HDT creates the Makefile:
Click Window > Preferences > VHDL > Makefiles, enable Mentor Modelsim (vsim) and confirm with OK

The Makefile is generated when you perform a full (re)build of your project. Click Project > Rebuild project to force this build. The Makefile.vsim should appear in the Project Explorer now.

Next you have to add a builder to your project that will automatically execute the Makefile.

Right-click your project (the dlx-project in this example) and select Properties > Builders.

Click New...

Select Program as Configuration Type

Next, configure the builder:

  • Give your builder a name: e.g. ModelSim.
  • Enter "/usr/bin/make" as the location of the program to run.
  • Click Select Workspace to set the Working Directory and select the root of your project (${workspace_loc:/dlx} for my project)
  • Next enter as arguments: --makefile=Makefile.vsim all

With the default settings the ModelSim Makefile will only be run during a manual build or after a "Clean". To make sure Sigas HDT runs make every time you save a changed file, click the build options tab and enable the During auto builds checkbox.

When you close the builder configuration dialog windows, make will automatically be run, and Modelsim's messages will appear in the console view.

Note that warnings and errors in the console are clickable. If you click a message, the corresponding location will automatically be opened in the Editor view.

Hendrik

P.S.: You can add as many extra builders as you want this way. E.g. for extra linting, code generators,...

Learning from LEON3/GRLIB (part 1/3)

The LEON3/GRLIB project from Airoflex Gaisler (formerly Gaisler Research) is one of the largest open source VHDL projects. It contains almost 700 VHDL files, for a total of 600.000 lines of code. The project is based on the AMBA on-chip bus and serves as a framework for building SoCs. It is used in consumer electronics, automotive and aerospace applications.

Free tutorial webinar on December 15th

You have downloaded and tried Sigasi HDT? You have discovered some of its nice features, but you have the feeling there is a lot more to explore? This free webinar shows you the most important productivity features, so you can make the most out of using the VHDL tool of the future: Sigasi HDT.

Free Webinar: A walk through Sigasi HDT

You have downloaded and tried Sigasi HDT? You have discovered some of its nice features, but you have the feeling there is a lot more to explore?

This free webinar shows you the most important productivity features, so you can make the most out of using the VHDL tool of the future: Sigasi HDT.

Sign up now, and join us on Wednesday, 2009-12-09 at 19:00 UTC.

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Hendrik.

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