internship

Graphical Integration with VHDL Simulators

This is a proposal for a thesis for Master of Engineering or Master of Science in Engineering students. In order to apply, please read the page on Internships and Thesis Proposals.

  • Project: Master of Science in Engineering thesis
  • Skills: Java, Eclipse
  • Target audience: electronics or computer science engineers

You will create a plugin that provides the link between Sigasi Pro and ModelSim, the most popular VHDL simulator on the market.

EDIF editor plugin for Eclipse

This is a proposal for a thesis for Master of Engineering or Master of Science in Engineering students. In order to apply, please read the page on Internships and Thesis Proposals.

  • Project: Master of Science in Engineering thesis
  • Skills: VHDL, Java, Eclipse, Xtext
  • Target audience: electronics or computer science engineers

You will write an Eclipse Plugin that acts as an EDIF editor and viewer.

HTML exporter for VHDL code

This is a proposal for a thesis for Master of Engineering or Master of Science in Engineering students. In order to apply, please read the page on Internships and Thesis Proposals.

  • Project: Master of Science in Engineering thesis
  • Skills: VHDL, Java, Eclipse
  • Target audience: electronics or computer science engineers

You will write an Eclipse Plugin that connects to the Sigasi VHDL plugin. Your plugin will be able to generate a set of HTML pages; one page for each VHDL file. The HTML pages will serve as browsable documentation.

Semantic HDL IP Cores Search Engine

This is a proposal for a Master/Bachelor of Engineering project. This project initiated by Vladimir Zdraveski of the University of Skopje, Macedonia. If you want to participate in this project, please visit the HDL IP Cores website.

  • Project: Master/Bachelor of Science in Engineering thesis
  • Skills: VHDL, Java, Eclipse
  • Target audience: computer science engineers

Recently, many system on chip designers started writing their own HDL components and made them freely available on the Internet.

Create the new VHDLUnit

This is a proposal for a Master of Science Engineering Thesis. In order to apply, please read the page on Internships and Thesis Proposals.

  • Project: Master of Science in Engineering thesis
  • Skills: VHDL, Java, Eclipse
  • Target audience: electronics or computer science engineers

Unit testing and test driven development are well established practices in software engineering. Most major programming languages have an xUnit implementation (JUnit for Java, PyUnit for Python and so on).

In hardware engineering, there are no widely accepted test driven methodologies. While most hardware design is done in programming languages (VHDL and Verilog), there is still no VHDLUnit framework.

Your mission is to create a VHDLUnit framework for VHDL. You will research the various xUnit implementations, talk to VHDL designers online and propose a new VHDLUnit. You will implement VHDLUnit in VHDL, with extra functionality in Java or scripting languages.

The best engineers have excellent communication skills. This thesis is not only about building a complex software product, but also about listening and talking to your end-users. If successful, you will have contributed to the way electronic engineering is taught and practiced.

Further reading.