Jan on HDL Design

In my previous blog post, I concluded that RTL synthesis was the latest of the all-time most important EDA innovations. Although it is more than 20 years old, nothing with a similar impact has happened since.

It's not that there was a lack of candidates. In the early nineties, several ideas and technologies seemed to have great potential. Personally, I was eager to repeat my great experience with RTL synthesis. Moreover, my company was basically selling design methodology, so we had a vested interest to stay at the forefront of innovation. Consequently, we were continuously watching out for the next big thing. But it didn't come. So here is my personal anti-list: the biggest EDA innovations that did not happen.

First on my list is Asynchronous Design Synthesis. Asynchronous design refers to design techniques without a global clock. It promises advantages with regard to performance, power consumption and design security, but it is inherently more complicated than synchronous design.

Then comes Formal Verification. Formal verification refers to the use of mathematical proof to verify the correctness of a design. When it works, it is superior to simulation, because it provides a 100% guarantee.

Last but not least we have Behavioral Synthesis. This is a technique whereby one starts from an algorithmic description, and where a synthesis tool allocates hardware resources and assigns operations to clock cycles.

Let me be clear about my position. I certainly don't want to suggest that there hasn't been any progress in the listed domains. Quite the contrary. There are now EDA tools that support a systematic methodology for asynchronous design. Formal verification tools are being employed successfully for certain well-defined tasks in the design flow. And behavioral synthesis is moving into the spotlight with the new wave of C-based high level synthesis tools.

What I am saying is that these tools have not fundamentally changed the way in which the majority of design engineers work. The mainstream paradigm for digital circuitry and EDA is still synchronous design. To verify the functionality of complex designs, we are still using good old simulation, not formal verification. And behavioral synthesis hasn't replaced RTL synthesis as the principal synthesis technique in mainstream design flows.

In summary, none of these tools has revolutionized the industry in the way RTL synthesis did.

In my previous blog post, I told you that back in 1990 I got pretty excited about my first experiments with Synopsys Design Compiler.

To understand my excitement better, let me explain where I was coming from. After I graduated in 1985, I had worked for 2.5 years at the brand new IMEC institute in Leuven, Belgium. I was part of a team that did research on behavioral synthesis, in a project called the Cathedral silicon compiler. I remember well how we thought about the state of the field. Logic synthesis was considered a solved problem. The next big thing was "obviously" going to be behavioral synthesis. However, this is a very complex problem. Therefore (so the argument went) you have to choose a particular application domain to make it tractable. In our case, the application domain was DSP.

There were several clever people in the team doing clever things. But I remember that I often got a feeling of dissatisfaction. The choice of an application domain seemed artificial and arbitrary. Moreover, our behavioral synthesis tool needed a lot of manual steering through so-called "pragma's". As a result, it often seemed that the tool was not just restricted to an application domain, but to a single example.

Synopsys Design Compiler was a totally different kind of tool. It didn't need to know about the application domain: you could use it for just about any kind of digital design. Moreover, it came up with a good solution by default: pragma's and settings were only required to further optimize an already good solution. I felt relieved: this was silicon compilation according to my taste!

I can hear the critique already. What's the point in comparing a research project on behavioral synthesis to a commercial tool that surely works at a much lower level? Isn't this comparing apples to oranges? Well, I have a lot more to say about that, but I'll leave it for future posts. But in some sense the critique is definitely valid. As a result, my main conclusion out of this experience was that I'm probably not suited for an academic career. I didn't realize it at the time, but what I missed was a direct link to industry and customers.

I guess I always felt more at ease in the bazaar than in the cathedral.

Next year, in 2010, my relationship with VHDL will be 20 years old. It has been a good journey, but I can't say that it was love at first sight.

The first chip I designed while at Alcatel was done with Verilog. I remember that I was quite happy with Verilog. However, at the time (1990) there was this idea that very soon VHDL would take over the whole market. I remember very well how that idea was cultivated by a start-up CAD company called Synopsys.

At a certain point, management decided to switch to VHDL. So I promptly wrote a memo explaining why that decision was wrong, and why Verilog would prosper, using the kind of pro-Verilog arguments that I have been reading over and over again since. I believe that is why I understand the pro-Verilog camp well: I was once part of it.

Over the years my relationship with Verilog deteriorated into a love-hate relationship that eventually ended with a separation with mutual consent. I just had too many bad surprises. I often felt that Verilog was like a nice looking building on very shaky foundations. Therefore, I eventually settled for the solid ground of VHDL's strong typing and delta cycle algorithm.

In retrospect, the pro-Verilog analysis in my memo to management wasn't wrong. Verilog really has prospered, even though the building doesn't look nice anymore because of too many additions from too many architects. However, management's decision to switch to VHDL wasn't wrong either. VHDL has prospered too.

Late 1991, I co-founded a design services company, and we faced the choice between Verilog and VHDL. Our strong point was a methodology based on the vision that I presented in my previous blog post: digital hardware design is a kind of software development. We concluded that VHDL was a better language to support that vision. And in fact, VHDL has kept its promises and things have turned out pretty well. VHDL has been a good choice for us.