Sigasi HDT Release Notes

Dear Sigasi HDT user,

In this release we worked hard to improve overall usability of Sigasi HDT to enhance your VHDL development experience. The major improvements are autocompletion for records and the severity of problem markers is now configurable.

We implemented a first version of autocomplete for records, which covers 90% of all use cases. You have to save the VHDL file once after you declare a signal, constant or variable of a record type, before you can use autocomplete for it. Autocomplete for records is automatically triggered when you type the '.'.

We also added a preference dialog for changing the severity of problem markers.
This is especially handy if you want to ignore certain linting warnings (such as the warning for deprecated libraries).

Other noteworthy changes:

• The documentation is now also available online (announcement).
• Linked resources are now supported in the automatic Makefile generation (ticket:674).
• Better error message when you use c-style equal "==" and not-equal "!=". This is a typical error for newcomers and developers that have to change language frequently.

  

• Bug fix for ticket ticket:708 which resulted in an incorrect unused signal warning.
• Based on user feedback, the align action now ignores empty and comment lines.
• Occurrence highlighting is now disabled when an editor contains changes to avoid confusion (ticket:733).
• Improved occurrence highlighting for aliases (ticket:408)

Let us know what you think about this new release in the comments or on our forum.

The Sigasi team.

P.S.: If you never did an update before, see the FAQ for more information on updates.

Dear Sigasi HDT user,

We are proud to announce the official 1.0 release of Sigasi HDT, the compelling next-generation development environment for VHDL designers.

Thanks to a lot of valuable comments and feedback trough a very successful public beta program, Sigasi HDT 1.0 has
a relevant and mature feature set:

Intelligent navigation

Navigate to any VHDL object in the design by selecting it in a hierarchical view. Or directly navigate from an object to its declaration.

Instant error reporting

Get immediate feedback on errors introduced by a modification.

Intelligent code completion

Use the tool to assist in completing VHDL constructs based on its knowledge of the design.

Quickfixes

Fix errors by using a quickfix proposed by the tool.

Design Flow Integration

Sigasi HDT allows integration in any toolflow. Automatic Makefile generation for ModelSim is supported out of the box.

Refactoring

Use the tool to make sophisticated code transformations that maintain the behavior of the design.

All these features create a novel user experience that greatly improves productivity.

This release marks the end of the beta program. Please be aware all beta licenses are about to expire. To ensure you are able to continue to use Sigasi HDT, you can purchase a license from our website.

The Sigasi Team.

P.S.: If you never did an update before, see the FAQ for more information on updates.

Dear Beta user,

With this release we introduce the first real integration with an external tool: ModelSim (vsim). We added an option to automatically generate a Makefile for your project that correctly reflects the real dependencies between design files (in VHDL terms) even if your design consists of multiple VHDL libraries. This results in the shortest recompile times when design files are changed.

We invite you to experiment with this new feature and give us your feedback so we can improve it and extend it to more external tools.

The integration does not stop with generating a solid make file. You can also run make from within Sigasi HDT. The output of vsim will be automatically piped to Sigasi HDT's console view. If vsim reported warnings or errors, these messages are rendered as hyperlinks to easily navigate to the corresponding code in Sigasi HDT (see also this feature request on our forum).

To encourage the use of VHDL libraries to organize your projects. We now clearly mark each VHDL file and folder with the name of the library they belong to.

This release also resolves a lot of reported issues:

• Fixed a bug in our design file dependency analyzer (ticket:59): A direct architecture instantiation now triggers a dependency on the instantiated architecture. This is important if the entity and architecture are not in the same file.
• Fixed a problem with use clauses in declarative parts (ticket:647).
• Provide hovering info for based literals such as 16#11#
  
• VHDL does not allow identifiers that start or end with an underscore, or that contain two consecutive underscores. We improved the way we handle these illegal identifiers. Error markers and messages are much clearer now.
  
• Fixed bug in hierarchy view: double click in hierarchy view failed for external files
• Improved responsiveness of the VHDL context sensitive search.
• Make it more clear when the declare signal quickfix could not guess the datatype:
  The declare signal quickfix guesses the datatype of the undeclared signal. If no good guess can be made, the default value is now __datatype__. Since this is not a valid VHDL identifier, you know that you have to fix it later.

Please let us know what you think about this new release on our user forum.

The Sigasi Team.

P.S.: If you never did an update before, see the FAQ for more information on updates.