Integration with Xilinx ISim HDL Simulator

This video demonstrates the integration of Sigasi Pro with the Xilinx ISim HDL Simulator. Each time you save a file, ISim kicks in and compiles your file. Any errors that ISim finds are displayed in your VHDL editor view, right next to the offending code. You can also start the Xilinx ISim HDL simulator right from Sigasi Pro.
Learn why save-time compilation helps you write better code faster.