Sigasi HDT Release Notes

Release notes from Sigasi HDT updates (Latest updates first).

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UPDATE 2010-08-24

Dear Sigasi HDT user,

in this release we implemented semantic highlighting. Semantic highlighting adds an extra layer of information in the VHDL editor based on the semantic meaning of the code.

Semantic highlightingSemantic highlighting

Signals, variables and constants now have different markup. This enables you to easily see what an identifier is, without scrolling, hovering or navigating to declarations.

Let us know what you think about this new release in the comments or on our forum.

The Sigasi Team.

New and noteworthy

  • Thanks to our internal VHDL compiler, we can now offer semantic highlighting in our VHDL editor, based on the true meaning of identifiers.
    Semantic highlighting (crazy example)Semantic highlighting (crazy example)

    The colors of the semantic highlighting can be customized in the same way you can customize syntax highlighting.

  • Syntax highlighting for VHDL code in compare views.
    Syntax highlighting in compare viewSyntax highlighting in compare view

Bug Fixes

  • ticket 862 Fixed bug in VHDL stuttering.
  • The tutorial project is now available as a download on our website. This allows the Eclipse plugin users to run the interactive tutorial too (and extend their trial license with an extra week).

P.S.

UPDATE 2010-07-27

Dear Sigasi HDT user,

in this release we updated Sigasi HDT's underlying Eclipse Platform to the Eclipse Helios release (a.k.a. Eclipse 3.6). This update brings a lot of framework improvements and bug fixes to the stand-alone version of Sigasi HDT.

If you use the Eclipse plugin version and prefer to keep working with Eclipse Galileo (Eclipse 3.5). Do not worry, the Sigasi HDT plugin is still 100% compatible with Eclipse Galileo.

Let us know what you think about this new release in the comments or on our forum.

The Sigasi Team.

New and noteworthy

  • Problem markers now remain visible in the rulers when they are inside folded regions.
  • Quick Access (Ctrl-3) now shows the keybindings of the commands you type.
  • The Resource Properties Page (Alt-Enter or via context menu in Project Explorer) now shows the full set of UNIX file permissions.
  • The Open Resource dialog (Ctrl-Shift-R) now supports path patterns, relative paths and puts the best matching items on top.
  • When you drag files and folders into the Project Explorer (from Windows Explorer, Finder,...), you now can choose whether the resources should be copied or linked.
  • Linked resources can now be changed in the Resource Properties page (click Edit... button).
  • And more: the complete list of new and noteworthy features in Eclipse Helios

Bug Fixes

  • ticket: 852 Lexer errors (such as those caused by non-ascii characters) should result in a marker on the correct line and column (forum topic).
  • Restored support for automatic Makefile generation in the Eclipse plugin version (forum topic).
  • ticket: 661 issue with windows focus after autocomplete (forum topic).

P.S.

UPDATE 2010-06-28

Dear Sigasi HDT user,

the heat wave through Belgium brings you another hot Sigasi HDT release. We present a new set of productivity enhancements and bug fixes.

Let us know what you think about this new release in the comments or on our forum.

The Sigasi Team.

New and noteworthy

  • For the former Emacs users we implemented stuttering. This allows to very rapidly type assignment symbols (=>,<=,:=) by 'double tapping' easy to reach keys on the keyboard (.,,,;).
  • We implemented a Fix Case action to clean up the use of upper and lower case usage in keywords and identifiers.
  • We added a "Set as Top Level" action to the outline and hiearchy view.
  • We implemented an intelligent quickfix to import Xilinx libraries as discussed on our forum.
  • In this release we also renamed the Color preference page to Editor, to better reflect it contents.

Bug Fixes

  • ticket:284: Detect clock edge when clock is element of array
  • ticket:722: Renaming an object that has an alias fails
  • ticket:780: No syntax error for missing "component" at the end of a component declaration
  • ticket:821: Hierarchy view should show generate statements, even when filtering
  • ticket:823: Align action does not deal with line ends correctly
  • ticket:827: Align should also remove internal whitespace
  • ticket:416: Initial support protected types
  • ticket:813: Better warning for multiple declarations in use clauses
  • ticket:819: Ask to save all editors before starting any external tool
  • ticket:820: RecognitionException when using alias

P.S.

Update 2010-05-17

Dear Sigasi HDT user,

In this release we have updated Sigasi HDT to support the new Xilinx ISE 12 release out of the box, improved the hierarchy view and closed a lot of pending tickets.

Let us know what you think about this new release in the comments or on our forum.

The Sigasi team.

New and noteworthy

  • Based on your feedback we implemented an instantiations filter and a sort button for the hierarchy view.

    You can now 'show instantiations only' and 'sort' the hierarchy viewYou can now 'show instantiations only' and 'sort' the hierarchy view

  • Sigasi HDT was updated to support the fresh Xilinx version 12.1 out of the box. So no more special case for using ISim version 12.1.

    Splash screen Xilinx ISim 12.1Splash screen Xilinx ISim 12.1

  • The library mapping interface has been extended so that it is now possible to map individual external files to a VHDL library. This was especially required if you want to use the Actel VHDL libraries, since each Actel library is contained in a single files and all libraries are distributed in a single folder by default.

    Map an individual external file to an external VHDL libraryMap an individual external file to an external VHDL library

  • Improved project related actions: In previous releases of Sigasi HDT project related actions (Rebuild, compile/run with ISim) were only enabled if the editor view showed a vhdl-file. Project related actions are now also enabled when the editor shows a different file type (as long as the file belongs to a vhdl project).

    Project menuProject menu

Bug Fixes

  • ticket:792: Incorrect unused declaration warning when records and arrays are used together
  • ticket:777: Problem with end of line characters
  • ticket:655 and ticket:783: Labels should be in the same scope as declarations (completely resolves the issues with attributes as reported on our forum)
  • Indent worked incorrect for dirty editors. Indent now asks to save first
  • ticket:778: Click certain ModelSim errors in the console log gave errors on Windows
  • ticket:782: Open matching Entity (Shift+F3) now also works for entity instantiations
  • ticket:84: Constants can not have same name as ports
  • ticket:776: Error in sensitivity list linting

P.S.

UPDATE 2010-04-19

Dear Sigasi HDT user,

In this release we present our first step towards integration with the Xilinx ISE (Integrated Synthesis Environment) tool suite. This release offers both import functionality for ISE projects and also allows to start the Xilinx ISE simulator from within Sigasi HDT.

Run Xilinx ISim from within Sigasi HDTRun Xilinx ISim from within Sigasi HDT

Import ISE projects

Sigasi HDT now supports setting up projects based on an existing Xilinx ISE project (the project.xise file). Just use the "Point to exiting project wizard" to point Sigasi HDT to the existing project. Sigasi HDT will automatically detect Xilinx project files (*.xise) and offer the import option.

Import Xilinx ISE project with the "Point to existing project wizard"Import Xilinx ISE project with the "Point to existing project wizard"

Sigasi HDT will parse the project file and automatically include and exclude the necesarry files. Libraries will also be set up.

In this first version of the Xilinx project importer, the importer only supports Xilinx projects with local files. Projects with design files outside the project folder are not supported yet.

Simulate with ISim

Xilinx now ships its own HDL simulator with ISE, that enables functional and timing simulations for VHDL, Verilog and mixed VHDL/Verilog designs: ISim. update: read about Xilinx and Modelsim

This release allows to compile and run your design with ISim from within Sigasi HDT: just click Project > Compile with ISim and Sigasi HDT creates the necessary scripts to run your project with ISim. You can use these scripts as inspiration to write headless simulation scripts.

As with the ModelSim output, links in console log are clickable and point the editor view to the corresponding location.

Console output ISimConsole output ISim

Of course you need to have Xilinx ISE installed (Sorry Mac Os X users).

Other noteworthy changes:

  • We simplified the icons used for the VHDL-specific views.

    New IconsNew Icons

  • The hierarchy view has been completely refactored. The hierarchy view is now a fixed view for an entire project with a configurable top level.

    New hierarchy view. Notice the "Select Toplevel..." menu itemNew hierarchy view. Notice the "Select Toplevel..." menu item

  • Improved error recovery of our VHDL parser and analyzer.

    Better recovery from syntax errors. The outline and navigation works as if the syntax were correct.Better recovery from syntax errors. The outline and navigation works as if the syntax were correct.

  • Bug fixes:
    • ticket:753: dependencies are broken when directly instantiating an entity/architecture from another library
    • ticket:741: VSIM errors for linked files should also be clickable
    • ticket:746: alias in with/select throws null pointer exception

Let us know what you think about this new release in the comments or on our forum.

The Sigasi team.

P.S.:

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