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The future of VHDL design

Support links

  • get started: download Sigasi HDT and get your license key
  • FAQ: frequently asked questions
  • forum: discuss Sigasi HDT, suggest improvements, file bug reports and share tips and tricks
  • screencasts: see Sigasi HDT in action
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Recent content

Title New comments
The most needed EDA innovation
selected signal assignments
linked resources and Makefile.vsim
Autocomplete for VHDL records
Autocompletion for records
Vertical align
Vertical align (updated)
Unexpected Result When Using the Align Action
Pictures from last Belgian Eclipse Users Group
UPDATE 2010-03-05
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