Writing Finite State Machines

Write an entire case statement for your VHDL state machine with just a few key strokes. Use autocomplete (CTRL+SPACE) to generate an entire case statement. Then use CTRL+Click to jump from one state to another in the VHDL case-statement. We call this: "open matching when clause".
Update: discover more in a newer version of this screencast

Using Custom Templates in Sigasi 2

In a previous blog post, Using Autocomplete Templates in Sigasi HDT, I introduced autocomplete templates in Sigasi 2 and demonstrated how to use the pre-defined templates. In this post I'll explain how to customize these templates and how to create your own. Chances are high that the pre-defined templates slightly differ from your preferred style or that you have your own standard pieces of code that you use on a regular basis.


Create a testbench with Sigasi's autocomplete feature

Writing a testbench skeleton is easy with Sigasi's autocomplete feature. Just keep pressing Ctrl+Space. There are powerful autocomplete templates for:
  • VHDL entity / architecture skeleton
  • VHDL component declaration
  • VHDL instantions of component or entity
  • signal declarations
  • and much more

Record Autocomplete

If you work with VHDL records, you might find yourself clicking through files to find the names of record elements. Those days have past. Sigasi's record autocomplete features tells you exactly which record elements are available.

Context sensitive templates

Because your code gets analyzed as you type, Sigasi knows the region of code that you are editing. The content assist feature (a.k.a. autocomplete) is fully aware of the context and tries to offer you only the relevant templates.

Templates are sensitive to the context of your code. If you type the word "component" inside a VHDL declarative region, Sigasi offers a template for the VHDL component declaration, based on your existing entities. If you type the same word, component in the body of an architecture, Sigasi offers a component instantiation.

Likewise, if in the architecture body can expand to an if-generate statement, which is a concurrent statement. In a process, this will expand to an if-then statement, which is a sequential statement.