I have blogged before on how to import Xilinx ISE projects in Sigasi before. In this blog post I show how you can import an existing Vivado project into Sigasi.
If you have a Vivado project which uses one or more IP cores, the project becomes complex quickly. Vivado generates different sources for Simulation and Synthesis. And although VHDL has elegant support for this –entities can have multiple architectures–, Vivado generates duplicate entities instead.
Although project setup in Sigasi is in most cases straight forward, it remains a hurdle, certainly if you already have a 'project definition' in another tool. I have blogged about Scripting Sigasi project creation for importing custom project descriptions before. But now we extended the Python scripts to make even easier to import Xilinx ISE and Mentor Graphics HDL Designer projects. In this post I show how easy this has become.
When you start using Sigasi, the first thing you have to do is set up a Sigasi project. This consists of two steps: (1) selecting the VHDL files that you want in your project and (2) configuring in which VHDL library these files must be mapped. In most cases you already have this information in one form or another.