Jan on HDL Design

HDL design pioneer Jan DecaluweHDL design pioneer Jan Decaluwe

The personal view of HDL design pioneerJan Decaluwe on language-based hardware design. Aware of the past, but relevant for the future.

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Fixing Verilog is easy

The example in my previous post has triggered some interesting responses, providing more than enough material for a follow-up post. VHDL designers beware, hardcore Verilog stuff ahead!

Wasting real time in zero time

One day, a few days before tape-out….

Suppose that you are the project leader for a large ASIC or FPGA design. (Maybe you are.) The project’s delivery milestone (a.k.a. tape-out) is due soon. There is a nice regression test suite that makes sure nothing breaks as bugs are being fixed. The suite runs for a couple of hours overnight. Developers are required to run some basic checks before checking in changes, but not the full regression suite as that would take too long.

One morning, it turns out that some tests have failed mysteriously.

Pitfalls for circuit girls

The Circuit Girl

Some time ago I heard about a video with FPGA design book recommendations by Jeri Ellsworth, who is also known as the Circuit Girl. I admit that the concept of circuit girls triggered my imagination. Somehow I feel like there should be more of those. Consequently, I checked out her video without further delay.

Time for reflection

Dear reader,

In my previous post, I announced further considerations about nondeterminism in Verilog. However, I am getting worried that you may be losing interest. As a visitor of the Sigasi site, you are likely a VHDL design professional, or aspiring to become one. Why should you care about Verilog? Moreover, you are probably a busy person, looking for productivity solutions in your day-to-day work. What is the relevancy of all this pseudo-philosophical talk about nondeterminism? Before continuing, I think I have to give you an indication of where I am heading.

VHDL's crown jewel

How VHDL preserves determinism

In this post, I would like to talk about VHDL’s crown jewel: how it preserves determinism in a concurrent language. Here is a figure of how it works: