Screencasts

Introducing VCOM integration in Sigasi

In the upcoming release, Sigasi will have integration with VSIM / VCOM compilers. In this video blog, we demonstrate how all compilation errors in your code are detected automatically by Aldec's Riviera-PRO, as soon as you save your file. Let us know what you think in the comments section, below.

Declare VHDL Signal or Variable

Sigasi 2.3.1 has a new feature: automatically declare a Signal or Variable. If you are using a signal or a variable, but you forgot to declare it, Sigasi can write the declaration for you in just two clicks!

Quick Intro to Sigasi

One minute introduction to Sigasi.

Hierarchy View

Three minute overview of the Sigasi Hierarchy Viewer.

Hierarchy take generic paramters into account

The Sigasi Hierarchy view (coming up in Sigasi 2.3, March 2012) takes generics into account when computing the design hierarchy. If you change one of the generic parameters, the hierarchy will change.