Posted Mon, 2013-09-09 19:46 by philippe.faes (Sigasi)
Beginning VHDL engineers, and advanced engineers too, can get confused about the exact scope of a use clause and a library clause in VHDL. They usually show up at the top of a file, which would make you think that they are visible in the entire file. Unfortunately, the truth is a bit more complex.
First a small disclaimer: we've read the VHDL Language Reference Manual more thoroughly than 99.99% of all engineers you are ever going to meet (and more than what will make even a die-hard language geek happy).
Posted Wed, 2013-06-19 14:49 by philippe.faes (Sigasi)
In many projects, some of the VHDL code is generated in one way or another. For instance, many projects manage their register map in one master file and generate their VHDL packages and C headers using some kind of tool (either commercial or an in house script).
This article deals with integrating such a script in the Sigasi Pro development environment, so that your generated files are always up to date.