Posts that will make you a better VHDL designer, regardless of the tools you use.

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"Use" and "Library" in VHDL

Beginning VHDL engineers, and advanced engineers too, can get confused about the exact scope of a use clause and a library clause in VHDL. They usually show up at the top of a file, which would make you think that they are visible in the entire file. Unfortunately, the truth is a bit more complex.

First a small disclaimer: we've read the VHDL Language Reference Manual more thoroughly than 99.99% of all engineers you are ever going to meet (and more than what will make even a die-hard language geek happy).

Writing Finite State Machines in VHDL

Set up your code generator in Sigasi

In many projects, some of the VHDL code is generated in one way or another. For instance, many projects manage their register map in one master file and generate their VHDL packages and C headers using some kind of tool (either commercial or an in house script).
This article deals with integrating such a script in the Sigasi Pro development environment, so that your generated files are always up to date.

No VHDL Plugin for IE or Chrome

There is no VHDL plugin for IE or Chrome. Not because it is not possible, but because there is no reason. There are two important points we’d like to make on this April Fools day:

No need for a single language

People who are smart enough to learn VHDL, are smart enough to learn JavaScript or PHP too. Likewise, people who can learn C or Java, can learn VHDL or Verilog too. There is no need be monogamous when it comes to programming languages.

Writing Finite State Machines

Write an entire case statement for your VHDL state machine with just a few key strokes. Use autocomplete (CTRL+SPACE) to generate an entire case statement. Then use CTRL+Click to jump from one state to another in the VHDL case-statement. We call this: "open matching when clause".
Update: discover more in a newer version of this screencast