Everybody who has been taught VHDL in college or in a company with senior colleagues has heard the following "wisdom":
Pysical types are for simulation only. They cannot be synthesized. [commonly heard claim – debunked in this article]
This is the kind of knowledge was somehow made up in the latter years of the Cold War and was passed down from one generation of digital design engineers to the next.
Before we investigate this claim, let's examine what VHDL physical types are. A physical type is defined by a range and a number of units.