VHDL Blog

Posts that will make you a better VHDL designer, regardless of the tools you use.

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No VHDL Plugin for IE or Chrome

Posted Mon, 2013-04-01 12:08 by philippe.faes (Sigasi)

There is no VHDL plugin for IE or Chrome. Not because it is not possible, but because there is no reason. There are two important points we’d like to make on this April Fools day:

No need for a single language

People who are smart enough to learn VHDL, are smart enough to learn JavaScript or PHP too. Likewise, people who can learn C or Java, can learn VHDL or Verilog too. There is no need be monogamous when it comes to programming languages.

Writing Finite State Machines

Posted Fri, 2013-01-18 11:09 by philippe.faes (Sigasi)
Write an entire case statement for your VHDL state machine with just a few key strokes. Use autocomplete (CTRL+SPACE) to generate an entire case statement. Then use CTRL+Click to jump from one state to another in the VHDL case-statement. We call this: "open matching when clause". [since Sigasi 2.11]

How well does your compiler support VHDL 2008?

Posted Tue, 2012-10-23 16:59 by philippe.faes (Sigasi)

While some design teams will stick to VHDL-93 until the sun burns out, some people are using as much of the new VHDL-2008 standard as is supported by their tools. Big question is: how much is actually supported by which tools?

Spoiler Alert: The market leader in VHDL 2008 is Aldec.

The script

I've created a small script that can test your compiler against a set of VHDL files to see which constructs are supported. This is very much a work in progress.

VHDL Physical Type is not Synthesizable, or is it? (part 2)

Posted Mon, 2012-10-15 21:27 by philippe.faes (Sigasi)

In a previous post I pointed out that VHDL synthesis tools can indeed synthesize VHDL physical types. In the example I gave, all computations with physical types were done at elaboration time, so that the synthesis tool does not really have to deal with physical types at all.

I choose a example that was too weak and I want to make that right. So here is my new claim:

VHDL synthesis of physical types works perfectly well.

Short and powerful: no "but", no "caveat".

VHDL Physical Type is not Synthesizable, or is it?

Posted Thu, 2012-10-11 12:55 by philippe.faes (Sigasi)

Everybody who has been taught VHDL in college or in a company with senior colleagues has heard the following "wisdom":

Pysical types are for simulation only. They cannot be synthesized. [commonly heard claim – debunked in this article]

This is the kind of knowledge was somehow made up in the latter years of the Cold War and was passed down from one generation of digital design engineers to the next.

Before we investigate this claim, let's examine what VHDL physical types are. A physical type is defined by a range and a number of units.