Sigasi's Blog

This website hosts blogs on multiple topics that relate to the world, work and lives of Sigasi team members.

Sigasi HDT
All blog posts related to our product, Sigasi HDT: tips and tricks, howtos, feature discussions, ...
Jan on HDL design
Jan's blog about his personal views on HDL design.
VHDL
Posts that will make you a better VHDL designer, regardless of the tools you use.
Developing for Eclipse
We develop on top of Eclipse, so we have some experience in this field. In this feed, we share some of this experience.

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VHDL 2008 bit-string literals: generating a test set

Posted Tue, 2012-02-07 16:43 by philippe.faes (Sigasi)

We're writing a translator that can interpret the VHDL-2008 style bit-string literals. Based on the Doulos website, it is easy to create a small test-set.

Anybody care to contribute a bunch of other test cases?

Xtext resource caching: loading resources 5 times faster

Posted Tue, 2012-01-31 10:54 by mark.christiaens (Sigasi)

Those who cannot remember the past are condemned to repeat it (George Santayana). I've always felt ambivalent about that quote. History never ever repeats itself exactly. In computer science on the other hand, it applies very well. In all our collective software applications, we recalculate the same results time and time again and are therefore faced with constant question to remember or not to remember. In this blog series, I'm going to talk about a cache for Xtext resources that we've developed over the past year.

Configuration files and Version control

Posted Thu, 2012-01-19 21:44 by philippe.faes (Sigasi)

If you are using a version control system (which you should!) for your hardware designs, you might occasionally run in to an unpleasant surprise. Settings files that stay the same may change anyway and if you change just one setting, the settings file may have changed completely.

Stability

Version control systems like CVS, Subversion (SVN), Git and Clearcase help you in tracking changes in files. While many project descriptor file formats are not meant to be modified by the user, they are text based. Hence, they should be ideally suited for a version control system.

Adding Altera_MF to your project (Cheat Sheet)

Posted Thu, 2012-01-05 11:25 by heeckhau (Sigasi)

I have created a Sigasi (Eclipse) Cheat Sheet to assist you in adding the Altera MegaFunctions (altera_mf) to your Sigasi project.

This Cheat Sheet will be part of the next release. But you can already run it today via:

  1. Click Help > Cheat Sheets..
  2. Click Enter the URL of a cheat sheet and
  3. Enter http://www.sigasi.com/sites/www.sigasi.com/files/AlteraMF.xml
  4. Click OK

This should make it easier to add Altera_MF to your project.

If you spot any typos/errors, let me know.

Hendrik.

Organizing VHDL project: One design in one folder

Posted Thu, 2011-12-29 09:43 by philippe.faes (Sigasi)

As discussed in a previous article, you can organize your VHDL files in many ways in Sigasi. The three recommended ways are:

  1. No organization
  2. One design in one folder (described in this article)
  3. Aggregation of reusable projects (coming soon)

This article deals with the "one design – one folder" way of organizing a project. The basic idea is that all of the files for your new hardware design are in one folder on your hard drive.