When I first learned VHDL, I bumped in to quite a few language quirks. Here is one thing that I learned the hard way: the scope of VHDL use clauses.

I figured out that you can put several entities or packagas in the same file. Now, usually people only put design units in the same file in pairs, like entity + architecture or package + package body.:

library

use

entity

architecture

library

use

package

package body

Note that the use clauses and library clauses are only written once at the top of the VHDL file.

I was talking to some engineering students the other day, as they were doing a VHDL lab. I noticed a case statement for state machine with named states (enumerated data type). All states were handled in their case statement, and still they put an others section in their code. I had a hard time explaining that this clause was useless. The students mumbled something about their professor eating them alive if they'd forget the others and problems with uninitialized stated and high-impedance state.

In the past months, we have made large efforts to make Emacs obsolete. After enquiring on some Emacs-friendly newsgroups, I can only conclude that we have indeed offered a better solution than Emacs, in most ways.

Of course, you can't win every battle and you probably shouldn't even try. Here are some things at which Emacs will always be better. We're not even going to try.

h2.