VHDL is a very verbose language. You have to type a lot to describe you design and there is often a lot of redundancy in what you write in VHDL. One of the purposes of using Sigasi HDT is to improve your productivity. So we developed a system to automatically type as much for you: templates.

Templates are pieces of code that occur frequently enough that you would like to be able to insert them with a few keystrokes. Templates result in small fragments of reusable code that have certain pieces left open for you to fill in.